A Completion Timeout occurs when a completion (Cpl) or completion with data (CplD) TLP is not returned after an AXI to PCIe memory read request, or after a PCIe Configuration Read/Write request. Completions must be received within the value set in the Device Control 2 register in the PCIe configuration space register. When a completion timeout occurs for a PCIe memory read request, AXI Bridge for PCIe Gen3 IP provides SLVERR response, while DMA/Bridge Subsystem for PCIe in Bridge Mode IP provides OKAY response with 0s data on the AXI4 memory mapped bus.