Interrupt Decode Register (Offset 0x138)

Interrupt Decode Register (Offset 0x138) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID

PG194

Release Date

2023-11-24

Version

3.0 English

The Interrupt Decode register (described in the following table) provides a single location where the host processor interrupt service routine can determine what is causing the interrupt to be asserted and how to clear the interrupt. Writing a 1'b1 to any bit of the Interrupt Decode register clears that bit except for the Correctable, Non-Fatal, and Fatal bits.

Follow this sequence to clear the Correctable, Non-Fatal, and Fatal bits:

Clear the Root Port Error FIFO (0x154) by performing first a read, followed by write-back of the same register.
Read Root Port Status/Control Register (0x148) bit 16, and ensure that the Error FIFO is empty.
Note: If the error FIFO is still not empty, repeat step 1 and step 2 until the Error FIFO is empty.
Write to the Interrupt Decode Register (0x138) with 1 to the appropriate error bit to clear it.

Important: An asserted bit in the Interrupt Decode register does not cause the interrupt line to assert unless the corresponding bit in the Interrupt Mask register is also set.

Table 1. Interrupt Decode Register
Bits	Name	Core Access	Description
0	Link Down	RW1C	Indicates that Link-Up on the PCI Express link was lost. Not asserted unless link-up had previously been seen.
1	Reserved	RO	Reserved
2	Reserved	RO	Reserved
3	Hot Reset	RW1C	Indicates a Hot Reset was detected (Only as Endpoint).
4	Reserved	RO	Reserved
7:5	Cfg Completion Status	RW1C	Indicates config completion status.
8	Cfg Timeout	RW1C	Indicates timeout on an enhanced configuration access mechanism (ECAM) access. (Only applicable to Root Port cores.)
9	Correctable	RW1C	Indicates a correctable error message was received. Requester ID of error message should be read from the Root Port FIFO. (Only applicable to Root Port cores.)
10	Non-Fatal	RW1C	Indicates a non-fatal error message was received. Requester ID of error message should be read from the Root Port FIFO. (Only applicable to Root Port cores.)
11	Fatal	RW1C	Indicates a fata l error message was received. Requester ID of error message should be read from the Root Port FIFO. (Only applicable to Root Port cores.)
15:12	Reserved	RO	Reserved
16	INTx Interrupt Received	RW1C	Indicates an INTx interrupt was received. Interrupt details should be read from the Root Port FIFO. (Only applicable to Root Port cores.)
17	MSI Interrupt Received	RW1C	Indicates an MSI(x) interrupt was received. Interrupt details should be read from the Root Port FIFO. (Only applicable to Root Port cores.)
19:18	Reserved	RO	Reserved
20	Slave Unsupported Request	RW1C	Indicates that a completion TLP was received with a status of 0b001 - Unsupported Request.
21	Slave Unexpected Completion	RW1C	Indicates that a completion TLP was received that was unexpected.
22	Reserved	RO	Reserved. This bit previously indicates Slave Completion Timeout in the Bridge IP. This functionality is now maintained by the PCIe IP. See Slave Bridge Abnormal Conditions Completion Timeout section for details. The read request that has timed out.
23	Slave Error Poison	RW1C	Indicates the error poison (EP) bit was set in a completion TLP.
24	Slave Completer Abort	RW1C	Indicates that a completion TLP was received with a status of 0b100 - Completer Abort.
25	Slave Illegal Burst	RW1C	Indicates that a burst type other than INCR was requested by the AXI master.
26	Master DECERR	RW1C	Indicates a Decoder Error (DECERR) response was received.
27	Master SLVERR	RW1C	Indicates a Slave Error (SLVERR) response was received.
28	Reserved	RO	Reserved
31:29	Reserved	RO	Reserved