| AMD LogiCORE™ IP Facts Table | |||||
|---|---|---|---|---|---|
| Core Specifics | |||||
| Supported Device Family |
AXI
Bridge for PCIe Gen3: AMD UltraScale™
, AMD Virtex™ 7 XT
1
DMA/Bridge Subsystem for PCIe in AXI Bridge mode: AMD UltraScale+™ |
||||
| Supported User Interfaces | AXI4 | ||||
| Resources | Performance and Resource Utilization web page | ||||
| Provided with Core | |||||
| Design Files | Verilog | ||||
| Example Design | Verilog | ||||
| Test Bench | Verilog | ||||
| Constraints File | Xilinx Design Constraints (XDC) | ||||
| Simulation Model | Not Provided | ||||
| Supported S/W Driver | Root Port Driver | ||||
| Tested Design Flows 2 | |||||
| Design Entry | AMD Vivado™ Design Suite | ||||
| Simulation | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). | ||||
| Synthesis | Vivado synthesis | ||||
| Support | |||||
| Release Notes and Known Issues | Master Answer Record: 61898 | ||||
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 | ||||
| Support web page | |||||
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