Because many features in the Bridge core design can be parameterized, you can uniquely tailor the implementation of the core using only the resources required for the desired functionality. This approach also achieves the best possible performance with the lowest resource usage.
The parameters defined for the Bridge are shown in the following table.
Generic | Parameter Name | Description | Allowable Values | Default Value |
---|---|---|---|---|
Bridge Parameters | ||||
PCIE_BLK_LOCN | PCIe® integrated block location within FPGA | 0: X0Y0 1: X0Y1 2: X0Y2 3:X0Y3 4:X0Y4 1 5:X0Y5 1 |
0 | |
PL_UPSTREAM_FACING | Configures the AXI bridge for PCIe to be a Root Port or an Endpoint | TRUE: Endpoint FALSE: Root Port |
TRUE | |
G3 | C_COMP_TIMEOUT | Selects the slave bridge completion timeout counter value. This parameter is now deprecated. Completion timeout is now maintained by the PCIe IP. | 0: 50 µs 1: 50 ms | 0 |
G6 | C_AXIBAR_NUM | Number of AXI address apertures that can be accessed | 1: BAR_0 enabled 2: BAR_0, BAR_1 enabled 3: BAR_0, BAR_1, BAR_2 enabled 4: BAR_0 through BAR_3 enabled 5: BAR_0 through BAR_4 enabled 6: BAR_0 through BAR_5 enabled |
6 |
G7 | C_AXIBAR_0 | AXI BAR_0 aperture low address | Valid AXI address 3 4 | 0x00000000_00000000 |
G8 | C_AXIBAR_HIGHADDR_0 | AXI BAR_0 aperture high address | Valid AXI address 3 4 | 0x00000000_00000000 |
G10 | C_AXIBAR2PCIEBAR_0 | Initial address translation from an AXI BAR_0 address to a PCI Express address | Valid address for PCIe 2 | 0x00000000_00000000 |
G11 | C_AXIBAR_1 | AXI BAR_1 aperture low address | Valid AXI address 3 , 4 | 0x00000000_00000000 |
G12 | C_AXIBAR_HIGHADDR_1 | AXI BAR_1 aperture high address | Valid AXI address 3 , 4 | 0x00000000_00000000 |
G14 | C_AXIBAR2PCIEBAR_1 | Initial address translation from an AXI BAR_1 address to a PCI Express address | Valid address for PCIe 2 | 0x00000000_00000000 |
G15 | C_AXIBAR_2 | AXI BAR_2 aperture low address | Valid AXI address 3 , 4 | 0x00000000_00000000 |
G16 | C_AXIBAR_HIGHADDR_2 | AXI BAR_2 aperture high address | Valid AXI address 3 , 4 | 0x00000000_00000000 |
G18 | C_AXIBAR2PCIEBAR_2 | Initial address translation from an AXI BAR_2 address to a PCI Express address | Valid address for PCIe 2 | 0x00000000_00000000 |
G19 | C_AXIBAR_3 | AXI BAR_3 aperture low address | Valid AXI address 3 , 4 | 0x00000000_00000000 |
G20 | C_AXIBAR_HIGHADDR_3 | AXI BAR_3 aperture high address | Valid AXI address 3 , 4 | 0x00000000_00000000 |
G22 | C_AXIBAR2PCIEBAR_3 | Initial address translation from an AXI BAR_3 address to a PCI Express address | Valid address for PCIe 2 | 0x00000000_00000000 |
G23 | C_AXIBAR_4 | AXI BAR_4 aperture low address | Valid AXI address 3 , 4 | 0x00000000_00000000 |
G24 | C_AXIBAR_HIGHADDR_4 | AXI BAR_4 aperture high address | Valid AXI address 3 , 4 | 0x00000000_00000000 |
G26 | C_AXIBAR2PCIEBAR_4 | Initial address translation from an AXI BAR_4 address to a PCI Express address | Valid address for PCIe 2 | 0x00000000_00000000 |
G27 | C_AXIBAR_5 | AXI BAR_5 aperture low address | Valid AXI address 3 , 4 | 0x00000000_00000000 |
G28 | C_AXIBAR_HIGHADDR_5 | AXI BAR_5 aperture high address | Valid AXI address 3 , 4 | 0x00000000_00000000 |
G30 | C_AXIBAR2PCIEBAR_5 | Initial address translation from an AXI BAR_5 address to a PCI Express address | Valid address for PCIe 2 | 0x00000000_00000000 |
G31 | PCIEBAR_NUM | Number of address for PCIe apertures that can be accessed |
1: BAR_0 enabled 2: BAR_[0:1] enabled or BAR_1 as 64-bit 3: BAR_[0-2] enabled 4: BAR_[0-3] enabled or BAR_2 as 64-bit 5: BAR_[0-4] enabled or 6: BAR_[0-5] enabled or BAR_4 as 64-bit |
3 |
G33 | PF0_BAR0_APERTURE_SIZE | Specifies the size of the PCIe BAR |
0x05: 4 Kilobytes 0x06: 8 Kilobytes ... 0x0C: 512 Kilobytes 0x0D: 1 Megabyte ... 0x16: 512 Megabytes 0x17: 1 Gigabyte ... 0x1F: 256 Gigabytes |
0x05 |
PF0_BAR0_CONTROL | PCI Express control settings for BAR0 |
bit 0: 32-bit addressable = 0 64-bit addressable = 1 bit 1: Prefetchable off = 0 Prefetchable on = 1 bit 2: IO BAR = 0 Memory bar = 1 |
100 | |
G34 | C_PCIEBAR2AXIBAR_0 | Initial address translation from an AXI BAR_0 address to a PCI Express address | Valid AXI address | 0x00000000_00000000 |
G35 | PF0_BAR1_APERTURE_SIZE | Specifies the size of the PCIe BAR. |
0x05: 4 Kilobytes 0x06: 8 Kilobytes ... 0x0C: 512 Kilobytes 0x0D: 1 Megabyte ... 0x16: 512 Megabytes 0x17: 1 Gigabyte ... 0x1F: 256 Gigabytes |
0x05 |
PF0_BAR1_CONTROL | PCI Express control settings for BAR1 |
bit 0: 32-bit addressable = 0 64-bit addressable = 1 bit 1: Prefetchable off = 0 Prefetchable on = 1 bit 2: IO bar = 0 Memory bar = 1 |
100 | |
G36 | C_PCIEBAR2AXIBAR_1 | Initial address translation from an AXI BAR_1 address to a PCI Express address | Valid AXI address | 0x00000000_00000000 |
G37 | PF0_BAR2_APERTURE_SIZE | Specifies the size of the PCIe BAR. |
0x05: 4 Kilobytes 0x06: 8 Kilobytes ... 0x0C: 512 Kilobytes 0x0D: 1 Megabyte ... 0x16: 512 Megabytes 0x17: 1 Gigabyte ... 0x1F: 256 Gigabytes |
0x05 |
PF0_BAR2_CONTROL | PCI Express control settings for BAR2 |
bit 0: 32-bit addressable = 0 64-bit addressable = 1 bit 1: Prefetchable off = 0 Prefetchable on = 1 bit 2: IO bar = 0 Memory bar = 1 |
100 | |
G38 | C_PCIEBAR2AXIBAR_2 | Initial address translation from an AXI BAR_2 address to a PCI Express address. | Valid AXI address | 0x00000000_00000000 |
PF0_BAR3_APERTURE_SIZE | Specifies the size of the PCIe BAR. |
0x05: 4 Kilobytes 0x06: 8 Kilobytes ... 0x0C: 512 Kilobytes 0x0D: 1 Megabyte ... 0x16: 512 Megabytes 0x17: 1 Gigabyte ... 0x1F: 256 Gigabytes |
0x05 | |
PF0_BAR3_CONTROL | PCI Express control settings for BAR3 |
bit 0: 32-bit addressable = 0 64-bit addressable = 1 bit 1: Prefetchable off = 0 Prefetchable on = 1 bit 2: IO bar = 0 Memory bar = 1 |
100 | |
C_PCIEBAR2AXIBAR_3 | Initial address translation from an AXI BAR_3 address to a PPCI Express address. | Valid AXI address | 0x00000000_00000000 | |
PF0_BAR4_APERTURE_SIZE | Specifies the size of the PCIe BAR. |
0x05: 4 Kilobytes 0x06: 8 Kilobytes ... 0x0C: 512 Kilobytes 0x0D: 1 Megabyte ... 0x16: 512 Megabytes 0x17: 1 Gigabyte ... 0x1F: 256 Gigabytes |
0x05 | |
PF0_BAR4_CONTROL | PCI Express control settings for BAR4 |
bit 0: 32-bit addressable = 0 64-bit addressable = 1 bit 1: Prefetchable off = 0 Prefetchable on = 1 bit 2: IO bar = 0 Memory bar = 1 |
100 | |
C_PCIEBAR2AXIBAR_4 | Initial address translation from an AXI BAR_4 address to a PCI Express address. | Valid AXI address | 0x00000000_00000000 | |
PF0_BAR5_APERTURE_SIZE | Specifies the size of the PCIe BAR. |
0x05: 4 Kilobytes 0x06: 8 Kilobytes ... 0x0C: 512 Kilobytes 0x0D: 1 Megabyte ... 0x16: 512 Megabytes 0x17: 1 Gigabyte ... 0x1F: 256 Gigabytes |
0x05 | |
PF0_BAR5_CONTROL | PCI Express control settings for BAR5 |
bit 0: 32-bit addressable = 0 64-bit addressable = 1 bit 1: Prefetchable off = 0 Prefetchable on = 1 bit 2: IO bar = 0 Memory bar = 1 |
100 | |
C_PCIEBAR2AXIBAR_5 | Initial address translation from an AXI BAR_5 address to a PCI Express address. | Valid AXI address | 0x00000000_00000000 | |
C_MSI_RX_PIN_EN | DMA/Bridge Subsystem for PCIe in AXI Bridge Mode only. Selects Legacy Interrupt FIFO mode or Interrupt Decode mode for Root Port configuration. |
0: Legacy Interrupt FIFO mode 1: Interrupt Decode mode |
0 | |
INTERRUPT_OUT_WIDTH | DMA/Bridge Subsystem for PCIe in AXI Bridge Mode only. Interrupt_out signal bus width. |
1: 1-bit for Legacy Interrupt FIFO mode or Endpoint configuration 3: 3-bits for Interrupt Decode mode |
1 | |
SOFT_RESET_EN | DMA/Bridge Subsystem for PCIe in AXI Bridge Mode
only. Enables the dma_bridge_resetn pin which allow user reset of all
internal Bridge engines and registers as well as all peripherals in
AXI domain while maintaining PCIe link up. |
TRUE: Enables FALSE: Disables |
FALSE | |
AXI4-Lite Parameters | ||||
G39 | C_BASEADDR | Device base address AXI Bridge for PCIe Gen3: When configured as an Root Port (RP), the minimum alignment granularity must be 256MB. Bit [27:0] is used for Bus Number, Device Number, Function number. For Endpoint, the minimum alignment granularity is 4KB. C_BASEADDR is deprecated for DMA/Bridge Subsystem for PCIe in AXI Bridge Mode. |
Valid AXI address | 0xFFFF_FFFF |
G40 | C_HIGHADDR | Device high address | Valid AXI address | 0x0000_0000 |
PCIe Core Configuration Parameters | ||||
G41 | PL_LINK_CAP_MAX_LINK_WIDTH | Number of PCIe Lanes | 1, 2, 4, 8 | 1 |
G42 | PF0_DEVICE_ID | Device ID | 16-bit vector | 0x0000 |
G43 | PF0_VENDOR_ID | Vendor ID | 16-bit vector | 0x0000 |
G44 | PF0_CLASS_CODE | Class Code | 24-bit vector | 0x00_0000 |
G45 | PF0_REVISION_ID | Rev ID | 8-bit vector | 0x00 |
G46 | C_SUBSYSTEM_ID | Subsystem ID | 16-bit vector | 0x0000 |
G47 | C_SUBSYSTEM_VENDOR_ ID | Subsystem Vendor ID | 16-bit vector | 0x0000 |
G49 | REF_CLK_FREQ |
Reference Clock input frequency.
|
0: 100 MHz 1: 125 MHz 2: 250 MHz |
0 |
G55 | PL_LINK_CAP_MAX_LINK_ SPEED | Maximum PCIe link speed supported |
0: 2.5 GT/s 1: 5.0 GT/s 4: 8.0 GT/s |
0 |
TL_LEGACY_MODE_ ENABLE | Selects between Legacy PCIe Endpoint Device and regular PCIe Endpoint Device |
TRUE: Legacy PCIe Endpoint Device FALSE: PCIe Endpoint Device |
FALSE | |
CORE_CLK_FREQ | Core Clock Frequency. See CORE CLOCK Frequency for valid configurations |
1: 250 MHz 2: 500 MHz |
2 | |
PLL_TYPE | Specifies PLL being used. |
0: CPLL 1: QPLL0 2: QPLL1 |
0 | |
USER_CLK_FREQ | AXI Clock Frequency |
1: 62.5 MHz 2: 125 MHz 3: 250 MHz |
1 | |
PIPE_SIM | PIPE Simulation Enable/Disable |
TRUE: Enable PIPE Simulation FALSE: Disable PIPE Simulation |
FALSE | |
EXT_CH_GT_DRP | Enable/Disable Transceiver DRP Ports |
TRUE: EnableTransceiver Block DRP Ports FALSE: Disable Transceiver Block DRP Ports |
FALSE | |
PCIE3_DRP | Enable/Disable PCIe DRP Ports |
TRUE: Enable PCIe Block DRP Ports FALSE: Disable PCIe Block DRP Ports |
FALSE | |
DEDICATE_PERST | Use the dedicated PERST routing resources |
TRUE: Use dedicated PERST signal routing FALSE: Use fabric routing for PERST signal |
TRUE | |
SYS_RESET_POLARITY | System Reset Polarity. An Active-Low reset should be selected for designs utilizing PCIe edge connector |
0: Active-Low 1: Active-High |
0 | |
EN_TRANSCEIVER_STATUS_PORTS | Enable Additional Transceiver Control and Status Ports |
False: Do not add Transceiver debug ports TRUE: Add Transceiver debug ports |
FALSE | |
MSI_ENABLED | Enable/Disable MSI support |
TRUE: Enable MSI-Support FALSE: Disable MSI Support |
TRUE | |
DEV_PORT_TYPE | Selects PCI Express Device Type |
0: PCI Express Endpoint Device 1: Legacy PCI Express Endpoint Device |
0 | |
MSIX_EN | Enable/Disable MSI-X support |
TRUE: Enable MSI-X Support FALSE: Disable MSI-X Support |
FALSE | |
pf0_msix_cap_pba_bir | Value of Pending Bit Array BAR Indicator Register. Indicates which BAR is used for MSI-X Pending Bit Array. |
0: BAR0 1: BAR1 2: BAR2 3: BAR3 4: BAR4 5: BAR5 |
0 | |
pf0_msix_cap_pba_offset | Value of Pending Bit Array Offset Register. Indicates the address offset within the BAR where MSI-X Pending Bit Array starts. | 'h0000_0000 to 'h1FFF_FFFF | 'h0000_0000 | |
pf0_msix_cap_table_bir | Value of MSI-X Table BAR Indicator Register. Indicates which BAR is used for MSI-X table. |
0: BAR0 1: BAR1 2: BAR2 3: BAR3 4: BAR4 5: BAR5 |
0 | |
pf0_msix_cap_table_offset | Value of MSI-X Table Offset Register. Indicates the address offset within the BAR where MSI-X table starts. | 'h0000_0000 to 'h1FFF_FFFF | ‘h0000_0000 | |
pf0_msix_cap_table_size | Value of MSI-X Table Size Register. Indicates the size of MSI-X table. | 'h000 to 'h7FF | 'h000 | |
Memory Mapped AXI4 Parameters | ||||
G50 | AXI_DATA_WIDTH | AXI Bus Data width |
64 128 256 |
64 |
G51 | AXI_ADDR_WIDTH | AXI Bus Address width | 32-64 | 32 |
G52 | C_S_AXI_ID_WIDTH | AXI Slave Bus ID width | 4 | 4 |
G56 | PF0_INTERRUPT_PIN | Legacy INTX pin support/select |
0: No INTX support (setting for Root Port). 1: INTA selected 2: INTB selected 3: INTC selected 4: INTD selected 1,2,3,4: (only selectable when core in Endpoint configuration). |
0 |
C_S_AXI_SUPPORTS_NARROW_BURST | Enable/Disable Narrow Burst support on S_AXI interface. |
0: Narrow Burst support disabled 1: Narrow Burst support enabled |
0 | |
AXI4 Slave Interconnect Parameters 5 | ||||
G57 | C_S_AXI_NUM_WRITE | AXI Interconnect Slave Port Write Pipeline Depth |
8 Size of pipeline for active AXI AWADDR values to be stored in AXI slave bridge PCIe. |
8 |
G58 | C_S_AXI_NUM_READ | AXI Interconnect Slave Port Read Pipeline Depth |
8 Size of pipeline for active AXI ARADDR values to be stored in AXI slave bridge PCIe. |
8 |
EN_AXI_SLAVE_IF | AXI4 Slave Bus Enable/Disable |
TRUE: AXI4 Slave Bus is active FALSE: AXI4 Slave Bus is disabled |
TRUE | |
AXI4 Master Interconnect Parameters 5 | ||||
G59 | C_M_AXI_NUM_WRITE | AXI Interconnect master bridge write address issue depth |
8 Number of actively issued AXI AWADDR values on the AXI Interconnect to the target slave device(s). |
8 |
G60 | C_M_AXI_NUM_READ | AXI Interconnect master bridge read address issue depth |
8 Number of actively issued AXI ARADDR values on the AXI Interconnect to the target slave device(s). |
8 |
EN_AXI_MASTER_IF | AXI4 Master Bus Enable/Disable |
TRUE: AXI4 Master Bus is active FALSE: AXI4 Master Bus is disabled |
TRUE | |
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