Performance - 1.1 English

Advanced Encryption Standard (AES) Engine LogiCORE IP Product Guide (PG383)

Document ID
PG383
Release Date
2022-04-26
Version
1.1 English

For full details about performance and resource use, visit the Performance and Resource Use web page.

Maximum Frequencies

The core has been tested for all configurations at 250 MHz.

Latency

The latency information consists of two components: initial core readiness latency and the engine input-to-output latency. Depending on the variant of the AES algorithm being used, the readiness latency numbers vary. The number of cycles taken by the engine differ by one cycle between the high-throughput pipelined and the low-throughput variant. The core is designed to mask the readiness latency between successive data units by prefetching the key, IV, and other metadata in advance while processing the current packet. Thus, if the next unit’s keys are provided within a certain number of cycles of the core requesting them, the design can achieve zero cycle latency between successive units.

Table 1. Latency Table
Encryption/Decryption Throughput Mode Key Size AES Mode Key Expansion Latency 1 Input to Output Latency 2 Total Latency
Encryption High-Throughput Mode 256 XTS 17 15 32
ECB 1 15 16
192 ECB 1 13 14
128 XTS 13 11 24
ECB 1 11 12
Low-Throughput Mode 256 XTS 17 16 33
ECB 1 16 17
CFB128 1 16 17
192 ECB 1 14 15
CFB128 1 14 15
128 XTS 13 12 25
ECB 1 12 13
CFB128 1 12 13
Decryption High-Throughput Mode 256 XTS 31 15 46
ECB 15 15 30
CFB128 1 15 16
192 ECB 13 13 26
CFB128 1 13 14
128 XTS 23 11 34
ECB 11 11 22
CFB128 1 11 12
Low-Throughput Mode 256 XTS 31 16 47
ECB 15 16 31
CFB128 1 16 17
192 ECB 13 14 27
CFB128 1 14 15
128 XTS 23 12 35
ECB 11 12 23
CFB128 1 12 13
  1. From key acceptance to input data acceptance
  2. From input data acceptance to output data
Note: Input data is plain text for encryption and cipher text for decryption. Output data is cipher text for encryption and plain text for decryption.
Figure 1. Latency Example

The simulation waveform shows encryption latency for XTS mode with key size width of 256-bit.

Throughput

The high-throughput variant can achieve up to 128 Gb/s of throughput across packets for a 512-bit interface for packets of size 4 KB or greater. For smaller packets, performance is reduced based on their size. For applications that do not demand such performance, the low-throughput variant can be used which can run up to speeds of ~900 MB/s for a 512-bit interface. The throughput scales down based on the data width for both the variants.