This reference design contains two reconfigurable partitions (RP), and under each RP, there is an isolated module (IM). There is one more isolated module in the static region. The design uses a simple bare metal application running in PS to load partial bitstreams. The partial bitstreams are placed into a PS-DDR memory and loaded into the device using an application running on the Cortex®-A53. The application uses the xilfpga library to load the partial bitstreams through the Processor Configuration Access Port (PCAP). More information on the xilfpga library can be found in the Zynq UltraScale+ MPSoC: Software Developers Guide (UG1137).
The design static IM contains a MicroBlaze™ and the ICAP to show isolation capabilities. This lab uses the RTL files from Lab 7 of Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947). This lab operates with the assumption that the user is familiar with the DFX design creation, covered through the labs in Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947).
To implement this example design first create top level block design, create block design containers for the instances that needs to be converted to reconfigurable partitions, add reconfigurable modules, then using DFX wizard define configurations then run synthesis. After completion of Synthesis, enable IDF for initial config and second configuration RMs. Next step is to create a floorplan for the initial/first configuration and run VIV DRCs to ensure everything is fine and correct the floorplan if any violations are reported by the tool and save the design. Implement the first configuration and after successful implementation of the first configuration, run VIV DRCs and verify that no violations are reported. Launch the implementation for the second configuration and verify that there are no warnings or errors from the DRC report. Run pr verify and then generate bitstreams. Complete the following steps to implement the example design.