Open the synth dcp
for floorplanning the first
configuration (Config1). Ensure that the HD.ISOLATED is set to True for the following modules, .
- Assign package pins and I/O ports for the design. Run the
following command from the Tcl console to assign package pins and I/O
ports.
source ./sources/pins.xdc
-
Create Pblocks for Reconfigurable
Partitions. Create a Pblock for
rp1
and assign site ranges for the Pblock. Run the following command from the Tcl console to create a Pblock for therp1
.source ./sources/pb_rp_shift.xdc
- Similarly, create a Pblock for
rp2
by running the following command from the Tcl console.source ./sources/pb_rp_count.xdc
After running the floorplan, the device looks like Figure 1.
Figure 1. Device View after the RP Floorplan - Save the design. Run the DFX DRCs by opening Reports -> Report DRC…. Select DFX DRCs, and click OK
to run the DRCs.Figure 2. DFX DRCs Selection Window
After running the DFX DRCs, you can see there are no warnings or errors. There are two advisory messages. You can ignore those messages as they will resolve after creating the Pblock for the static region which is the
static_iso_wrapper
. - Draw Pblocks for the Isolated Modules.
- Draw a Pblock for the static Isolated Module which is the
static_iso_wrapper
. Run the following command from the Tcl console.source ./sources/pb_iso_wrapper.xdc
- Draw a Pblock for the isolated module shift (
iso_2
) inside the Reconfigurable Partitionrp1
. Run the following command from the Tcl console:source ./sources/pb_shift_right.xdc
- Draw a Pblock for the Isolated Module count (
iso_3
) inside of the Reconfigurable Partitionrp2
. Run the following command from the Tcl console:source ./sources/pb_count_up.xdc
- Save the constraints by saving the design.Note: Ignore the constraints order changed warning.
- Draw a Pblock for the static Isolated Module which is the
- Run VIV
DRCs. These are IDF DRCs which are updated for the IDF+DFX flow.
Under Report DRC, select and . Click OK to run the
DRCs.Figure 3. IDF+DFX DRCs Selection WindowNote: Do not select IDF_VIV2-5 and IDF_VIV2-6 as the design is not implemented yet. After the DRC run is completed you can see many IDF-4 violations, as shown in Figure 4.Figure 4. VIV Errors for PU Adjacency (IDF4_VIV2-4)
-
Correct the floorplan
violation. IDF highly recommends taking advantage of the highlighting features of the Vivado tools. The following Tcl script highlights all the Pblocks in the design:
Shading the Pblocks tells the user what resources are included in it. Although, shading is visible when the Pblock is selected, highlighting it helps for better visibility. Additionally, it helps to differentiate between different Pblocks. In a highlighted Pblock, resources that have color are added to the Pblock, and the regions that are black are not included.Set pblocks [get_pblocks *];set ci 1;foreach pblock $pblocks {highlight_objects -color_index [expr {1 + ($ci % 19)}] [get_pblocks $pblock]; incr ci}
Perform the following to correct the IDF violations.
- Click the first violation from the DRC report window.
This selects the violating Programmable Units (PU) in the device view.
Refer to
Isolation Design Flow for UltraScale+ FPGAs and Zynq
UltraScale+ MPSoCs (XAPP1335) for
details on PU. You can select multiple violations to see the
corresponding violating PUs.Figure 5. Violating PUs on Device View
- Zoom to the selected PU area. You can see there is no
fence between the nested IM inside of the RP and the static IM in a
vertical direction. IPU fence is needed here; the fence can either be
inside of the RP or outside of the RP.Figure 6. Violating PUs in Device View Zoomed
- Create a fence inside of the RP. Select the nested IM
Pblock, and drag the Pblock edge towards the right side, so that the 1PU
fence is created. Or, you can use the following
resize_pblock
command to change the Pblock boundaries.resize_pblock pblock_count -add {SLICE_X58Y241:SLICE_X75Y298 BUFCE_LEAF_X312Y16:BUFCE_LEAF_X407Y19 BUFCE_ROW_FSR_X77Y4:BUFCE_ROW_FSR_X102Y4 DSP48E2_X12Y98:DSP48E2_X14Y117 HARD_SYNC_X14Y8:HARD_SYNC_X19Y9 RAMB18_X7Y98:RAMB18_X9Y117 RAMB36_X7Y49:RAMB36_X9Y58} -remove {SLICE_X56Y241:SLICE_X75Y298 BUFCE_LEAF_X304Y16:BUFCE_LEAF_X407Y19 BUFCE_ROW_FSR_X76Y4:BUFCE_ROW_FSR_X102Y4 DSP48E2_X12Y98:DSP48E2_X14Y117 HARD_SYNC_X14Y8:HARD_SYNC_X19Y9 RAMB18_X7Y98:RAMB18_X9Y117 RAMB36_X7Y49:RAMB36_X9Y58} -locs keep_all
After changing the Pblock boundaries, the Pblock loses its coloring. You can rerun the command to color the Pblocks. After creating the fence, the Pblock boundary will be as shown in Figure 7.
Figure 7. Pblock Count Boundary After Creating the Fence - Similarly, create an 1PU fence between the static IM
Pblock and the nested shift Pblock. Drag the nested Pblock such that the
fence is inside of the RP. For the shift block, create a horizontal
fence and a vertical fence. You can drag the Pblock boundaries to create
the fence or use the following
resize_pblock
command.resize_pblock pblock_shift -add {SLICE_X58Y300:SLICE_X75Y358 BUFCE_LEAF_X312Y20:BUFCE_LEAF_X407Y23 BUFCE_ROW_FSR_X77Y5:BUFCE_ROW_FSR_X102Y5 DSP48E2_X12Y120:DSP48E2_X14Y141 HARD_SYNC_X14Y10:HARD_SYNC_X19Y11 RAMB18_X7Y120:RAMB18_X9Y141 RAMB36_X7Y60:RAMB36_X9Y70} -remove {SLICE_X56Y300:SLICE_X75Y359 BUFCE_LEAF_X304Y20:BUFCE_LEAF_X407Y23 BUFCE_ROW_FSR_X76Y5:BUFCE_ROW_FSR_X102Y5 DSP48E2_X12Y120:DSP48E2_X14Y143 HARD_SYNC_X14Y10:HARD_SYNC_X19Y11 RAMB18_X7Y120:RAMB18_X9Y143 RAMB36_X7Y60:RAMB36_X9Y71} -locs keep_all
The following figure shows the Pblock boundaries after creating the fence.
Figure 8. Pblock Shift Boundary After Creating the Fence - Re-run the VIV DRCs as mentioned in Step
6. Note: Advisories are reported as Violations in the report summary of the DRCs. This is common to all the DRCs and has nothing to do with the VIV DRCs. This is an issue with the way the error counts are reported and print the advisories without incrementing the error count.Note: There are no warnings or errors in the DRC report.
- Click the first violation from the DRC report window.
This selects the violating Programmable Units (PU) in the device view.
Refer to
Isolation Design Flow for UltraScale+ FPGAs and Zynq
UltraScale+ MPSoCs (XAPP1335) for
details on PU. You can select multiple violations to see the
corresponding violating PUs.
- Save the constraints by saving the design.