PCIe DMA Tab - 4.0 English

QDMA Subsystem for PCI Express Product Guide (PG302)

Document ID
PG302
Release Date
2022-05-20
Version
4.0 English

The PCIe DMA Tab is shown in the following figure.

Figure 1. PCIe DMA Tab
Descriptor Bypass for Read/Write (H2C/C2H)
Two options to select from.
Note: In this mode (Internal mode) DMA will not bypass any H2C or C2H descriptors.
Descriptor bypass and Internal
In this mode descriptor ports for bypass out and bypass in are both enabled. Based on the context settings H2C or C2H descriptors can be sent out on descriptor bypass out. User can send in descriptors on Descriptor bypass in ports.
C2H Stream Completion
C2H Stream Completion Color bits
Completion Color bit position in completion entry. There are seven registers available to program, from bit 0 to 511 (for 64 bytes completion). You can program the bits, and generate a BIT file. During the DMA transfer, the input pins s_axis_c2h_cmpt_ctrl_color_idx[2:0] determine which Color bit position to use. Default bit position 1 is selected in register 0.
C2H Stream Completion Error bits
Completion Error bit position in completion entry. There are seven registers available to program, from bit 0 to 511 (for 64 bytes completion). You can program the bits, and generate a BIT file. During a DMA transfer, the input pins s_axis_c2h_cmpt_ctrl_err_idx[2:0] determine which Error bit position to use. Default bit position 2 is selected in register 0.
Performance options
Pre-fetch cache depth
The Prefetch cache supports up to 64 Queues. Select one of 16 or 64 (default 16). The Prefetch cache can support that many active queues at any given time. When one active queue finishes fetch and delivers all the descriptors for the packets of that queue, it then releases cache entry for other active queues. A larger cache size supports more active queues, but the area will also increase.
CMPT Coalesce Max buffer
Completion (CMPT) Coalesce Max buffer supports up to 64 buffers. Select one of 16 or 32 (default 16). Each entry of the CMPT Coalesce Buffer coalesces multiple Completions (up to 64B) to form a single queue before writing to the host to improve bandwidth utilization. A deeper CMPT Coalesce Buffer allows coalescing within more queues, but will increase the area as a downside.
Data Protection
Parity Checking and end to end data protection. By default, data protection is not enabled.

When Data Protection is not enabled:

  • You do not need to give any CRC/ECC values on C2H data and the control interface.
  • This will not log any Error and will not drop any packet.
  • User should ground the ECC and CRC ports.
  • CMPT parity check is not affected by this parameter.
    Note: You must always give the parity on CMPT.
When Data Protection is enabled:
  • You must send CRC/ECC values on C2H data and the control interface.
  • If there is any ECC or CRC error, error bits will be logged and data packet will be sent to host.
  • If error interrupt is enabled, an interrupt will be sent to host.
  • FATAL error can be enabled in the QDMA_C2H_FATAL_ERR_ENABLE register.
    • QDMA_C2H_FATAL_ERR_ENABLE[0]: If this bit is set, all packets are dropped after an error occurs.
    • QDMA_C2H_FATAL_ERR_ENABLE[1]: If this bit is set, parity is inverted and an error packet is sent to PCIe.