Debugging the Design - 2022.2 English

Vivado Design Suite User Guide: Programming and Debugging (UG908)

Document ID
UG908
Release Date
2022-10-19
Version
2022.2 English

Debugging an FPGA or ACAP design is a multi-step, iterative process. Like most complex problems, it is best to break the FPGA or ACAP design debugging process down into smaller parts by focusing on getting smaller sections of the design working one at a time rather than trying to get the whole design to work at once. Iterating through the design flow by adding one module at a time and getting it to function properly in the context of the whole design is one example of a proven design and debug methodology. You can use this design and debug methodology in any combination of the following design flow stages:

  • RTL-level design simulation
  • Post-implemented design simulation
  • In-system debugging