Block RAM and FIFO Switching Characteristics

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS189)

Document ID
DS189
Release Date
2022-10-31
Revision
1.10 English
Table  30:   Block RAM and FIFO Switching Characteristics

Symbol

Description

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

Block RAM and FIFO Clock-to-Out Delays

TRCKO_DO and TRCKO_DO_REG

Clock CLK to DOUT output (without output register).(1)(2)

2.13

2.46

2.46

ns, Max

Clock CLK to DOUT output (with output register).(3)(4)

0.74

0.89

0.89

ns, Max

TRCKO_DO_ECC and TRCKO_DO_ECC_REG

Clock CLK to DOUT output with ECC (without output register).(1)(2)

3.04

3.84

3.84

ns, Max

Clock CLK to DOUT output with ECC (with output register).(3)(4)

0.81

0.94

0.94

ns, Max

TRCKO_DO_CASCOUT and TRCKO_DO_CASCOUT_REG

Clock CLK to DOUT output with cascade (without output register).(1)

2.88

3.30

3.30

ns, Max

Clock CLK to DOUT output with cascade (with output register).(3)

1.28

1.46

1.46

ns, Max

TRCKO_FLAGS

Clock CLK to FIFO flags outputs.(5)

0.87

1.05

1.05

ns, Max

TRCKO_POINTERS

Clock CLK to FIFO pointers outputs.(6)

1.02

1.15

1.15

ns, Max

TRCKO_PARITY_ECC

Clock CLK to ECCPARITY in ECC encode only mode.

0.85

0.94

0.94

ns, Max

TRCKO_SDBIT_ECC and TRCKO_SDBIT_ECC_REG

Clock CLK to BITERR (without output register).

2.81

3.55

3.55

ns, Max

Clock CLK to BITERR (with output register).

0.76

0.89

0.89

ns, Max

TRCKO_RDADDR_ECC and TRCKO_RDADDR_ECC_REG

Clock CLK to RDADDR output with ECC (without output register).

0.88

1.07

1.07

ns, Max

Clock CLK to RDADDR output with ECC (with output register).

0.93

1.08

1.08

ns, Max

Setup and Hold Times Before/After Clock CLK

TRCCK_ADDRA/ TRCKC_ADDRA

ADDR inputs.(7)

0.49/0.33

0.57/0.36

0.57/0.36

ns, Min

TRDCK_DI_WF_NC/ TRCKD_DI_WF_NC

Data input setup/hold time when block RAM is configured in WRITE_FIRST or NO_CHANGE mode.(8)

0.65/0.63

0.74/0.67

0.74/0.67

ns, Min

TRDCK_DI_RF/ TRCKD_DI_RF

Data input setup/hold time when block RAM is configured in READ_FIRST mode.(8)

0.22/0.34

0.25/0.41

0.25/0.41

ns, Min

TRDCK_DI_ECC/ TRCKD_DI_ECC

DIN inputs with block RAM ECC in standard mode.(8)

0.55/0.46

0.63/0.50

0.63/0.50

ns, Min

TRDCK_DI_ECCW/ TRCKD_DI_ECCW

DIN inputs with block RAM ECC encode only.(8)

1.02/0.46

1.17/0.50

1.17/0.50

ns, Min

TRDCK_DI_ECC_FIFO/ TRCKD_DI_ECC_FIFO

DIN inputs with FIFO ECC in standard mode.(8)

1.15/0.59

1.32/0.64

1.32/0.64

ns, Min

TRCCK_INJECTBITERR/ TRCKC_INJECTBITERR

Inject single/double bit error in ECC mode.

0.64/0.37

0.74/0.40

0.74/0.40

ns, Min

TRCCK_EN/TRCKC_EN

Block RAM enable (EN) input.

0.39/0.21

0.45/0.23

0.45/0.23

ns, Min

TRCCK_REGCE/ TRCKC_REGCE

CE input of output register.

0.29/0.15

0.36/0.16

0.36/0.16

ns, Min

TRCCK_RSTREG/ TRCKC_RSTREG

Synchronous RSTREG input.

0.32/0.07

0.35/0.07

0.35/0.07

ns, Min

TRCCK_RSTRAM/ TRCKC_RSTRAM

Synchronous RSTRAM input.

0.34/0.43

0.36/0.46

0.36/0.46

ns, Min

TRCCK_WEA/TRCKC_WEA

Write enable (WE) input (block RAM only).

0.48/0.19

0.54/0.20

0.54/0.20

ns, Min

TRCCK_WREN/ TRCKC_WREN

WREN FIFO inputs.

0.46/0.35

0.47/0.43

0.47/0.43

ns, Min

TRCCK_RDEN/ TRCKC_RDEN

RDEN FIFO inputs.

0.43/0.35

0.43/0.43

0.43/0.43

ns, Min

Reset Delays

TRCO_FLAGS

Reset RST to FIFO flags/pointers.(9)

0.98

1.10

1.10

ns, Max

TRREC_RST/TRREM_RST

FIFO reset recovery and removal timing.(10)

2.07/–0.81

2.37/–0.81

2.37/–0.81

ns, Max

Maximum Frequency

FMAX_BRAM_WF_NC

Block RAM (write first and no change modes) when not in SDP RF mode.

460.83

388.20

388.20

MHz

FMAX_BRAM_RF_
PERFORMANCE

Block RAM (read first, performance mode) when in SDP RF mode but no address overlap between port A and
port B.

460.83

388.20

388.20

MHz

FMAX_BRAM_RF_
DELAYED_WRITE

Block RAM (read first, delayed write mode) when in SDP RF mode and there is possibility of overlap between port A and port B addresses.

404.53

339.67

339.67

MHz

FMAX_CAS_WF_NC

Block RAM cascade (write first, no change mode) when cascade but not in RF mode.

418.59

345.78

345.78

MHz

FMAX_CAS_RF_
PERFORMANCE

Block RAM cascade (read first, performance mode) when in cascade with RF mode and no possibility of address overlap/one port is disabled.

418.59

345.78

345.78

MHz

FMAX_CAS_RF_
DELAYED_WRITE

When in cascade RF mode and there is a possibility of address overlap between port A and port B.

362.19

297.35

297.35

MHz

FMAX_FIFO

FIFO in all modes without ECC.

460.83

388.20

388.20

MHz

FMAX_ECC

Block RAM and FIFO in ECC configuration.

365.10

297.53

297.53

MHz

Notes:

1.TRCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters.

2.These parameters also apply to synchronous FIFO with DO_REG = 0.

3.TRCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters.

4.These parameters also apply to multi-rate (asynchronous) and synchronous FIFO with DO_REG = 1.

5.TRCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR.

6.TRCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT.

7.The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible.

8.These parameters include both A and B inputs as well as the parity inputs of A and B.

9.TRCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.

10.RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the slowest clock (WRCLK or RDCLK).