Device Pin-to-Pin Input Parameter Guidelines

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS189)

Document ID
DS189
Release Date
2022-10-31
Revision
1.10 English

All devices are 100% functionally tested. Values are expressed in nanoseconds unless otherwise noted.

Table  44:   Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks

Symbol

Description

Device

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)

TPSFD/ TPHFD

Full delay (legacy delay or default delay) global clock input and IFF(2) without MMCM/PLL with ZHOLD_DELAY on HR I/O banks.

XC7S6

2.76/–0.40

3.17/–0.40

3.17/–0.40

ns

XC7S15

2.76/–0.40

3.17/–0.40

3.17/–0.40

ns

XC7S25

2.67/–0.37

3.12/–0.37

3.12/–0.37

ns

XC7S50

2.66/–0.28

3.11/–0.28

3.11/–0.28

ns

XC7S75

2.91/–0.33

3.36/–0.33

3.36/–0.33

ns

XC7S100

2.91/–0.33

3.36/–0.33

3.36/–0.33

ns

XA7S6

2.76/–0.40

3.17/–0.40

N/A

ns

XA7S15

2.76/–0.40

3.17/–0.40

N/A

ns

XA7S25

2.67/–0.37

3.12/–0.37

N/A

ns

XA7S50

2.66/–0.28

3.11/–0.28

N/A

ns

XA7S75

2.91/–0.33

3.36/–0.33

N/A

ns

XA7S100

2.91/–0.33

3.36/–0.33

N/A

ns

Notes:

1.Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage.

2.IFF = Input flip-flop or latch.

Table  45:   Clock-Capable Clock Input Setup and Hold With MMCM

Symbol

Description

Device

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.(1)(2)

TPSMMCMCC/ TPHMMCMCC

No delay clock-capable clock input and IFF(3) with MMCM.

XC7S6

2.73/–0.59

3.27/–0.59

3.27/–0.59

ns

XC7S15

2.73/–0.59

3.27/–0.59

3.27/–0.59

ns

XC7S25

2.69/–0.61

3.21/–0.61

3.21/–0.61

ns

XC7S50

2.81/–0.62

3.35/–0.62

3.35/–0.62

ns

XC7S75

2.81/–0.62

3.36/–0.62

3.36/–0.62

ns

XC7S100

2.81/–0.62

3.36/–0.62

3.36/–0.62

ns

XA7S6

2.73/–0.59

3.27/–0.59

N/A

ns

XA7S15

2.73/–0.59

3.27/–0.59

N/A

ns

XA7S25

2.69/–0.61

3.21/–0.61

N/A

ns

XA7S50

2.81/–0.62

3.35/–0.62

N/A

ns

XA7S75

2.81/–0.62

3.36/–0.62

N/A

ns

XA7S100

2.81/–0.62

3.36/–0.62

N/A

ns

Notes:

1.Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage.

2.Use IBIS to determine any duty-cycle distortion incurred using various standards.

3.IFF = Input flip-flop or latch.

Table  46:   Clock-Capable Clock Input Setup and Hold With PLL

Symbol

Description

Device

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.(1)(2)

TPSPLLCC/ TPHPLLCC

No delay clock-capable clock input and IFF(3) with PLL.

XC7S6

3.07/–0.17

3.69/–0.17

3.69/–0.17

ns

XC7S15

3.07/–0.17

3.69/–0.17

3.69/–0.17

ns

XC7S25

3.04/–0.19

3.64/–0.19

3.64/–0.19

ns

XC7S50

3.15/–0.19

3.77/–0.19

3.77/–0.19

ns

XC7S75

3.15/–0.19

3.78/–0.19

3.78/–0.19

ns

XC7S100

3.15/–0.19

3.78/–0.19

3.78/–0.19

ns

XA7S6

3.07/–0.17

3.69/–0.17

N/A

ns

XA7S15

3.07/–0.17

3.69/–0.17

N/A

ns

XA7S25

3.04/–0.19

3.64/–0.19

N/A

ns

XA7S50

3.15/–0.19

3.77/–0.19

N/A

ns

XA7S75

3.15/–0.19

3.78/–0.19

N/A

ns

XA7S100

3.15/–0.19

3.78/–0.19

N/A

ns

Notes:

1.Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage.

2.Use IBIS to determine any duty-cycle distortion incurred using various standards.

3.IFF = Input flip-flop or latch.

Table  47:   Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO

Symbol

Description

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard.

TPSCS/TPHCS

Setup and hold of I/O clock.

–0.38/1.46

–0.38/1.73

–0.38/1.76

ns

Table  48:   Sample Window

Symbol

Description

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

TSAMP

Sampling error at receiver pins.(1)

0.64

0.70

0.70

ns

TSAMP_BUFIO

Sampling error at receiver pins using BUFIO.(2)

0.40

0.46

0.46

ns

Notes:

1.This parameter indicates the total sampling error of the Spartan-7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements include:

- CLK0 MMCM jitter

- MMCM accuracy (phase offset)

- MMCM phase shift resolution

These measurements do not include package or clock tree skew.

2.This parameter indicates the total sampling error of the Spartan-7 FPGAs DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of operation. These measurements do not include package or clock tree skew.