MMCM Switching Characteristics

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS189)

Document ID
DS189
Release Date
2022-10-31
Revision
1.10 English
Table  37:   MMCM Specification

Symbol

Description

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

MMCM_FINMAX

Maximum input clock frequency.

800.00

800.00

800.00

MHz

MMCM_FINMIN

Minimum input clock frequency.

10.00

10.00

10.00

MHz

MMCM_FINJITTER

Maximum input clock period jitter.

< 20% of clock input period or 1 ns Max

MMCM_FINDUTY

Allowable input duty cycle: 10—49 MHz.

25

25

25

%

Allowable input duty cycle: 50—199 MHz.

30

30

30

%

Allowable input duty cycle: 200—399 MHz.

35

35

35

%

Allowable input duty cycle: 400—499 MHz.

40

40

40

%

Allowable input duty cycle: > 500 MHz.

45

45

45

%

MMCM_FMIN_PSCLK

Minimum dynamic phase-shift clock frequency.

0.01

0.01

0.01

MHz

MMCM_FMAX_PSCLK

Maximum dynamic phase-shift clock frequency.

500.00

450.00

450.00

MHz

MMCM_FVCOMIN

Minimum MMCM VCO frequency.

600.00

600.00

600.00

MHz

MMCM_FVCOMAX

Maximum MMCM VCO frequency.

1440.00

1200.00

1200.00

MHz

MMCM_FBANDWIDTH

Low MMCM bandwidth at typical.(1)

1.00

1.00

1.00

MHz

High MMCM bandwidth at typical.(1)

4.00

4.00

4.00

MHz

MMCM_TSTATPHAOFFSET

Static phase offset of the MMCM outputs.(2)

0.12

0.12

0.12

ns

MMCM_TOUTJITTER

MMCM output jitter.

Note 3

MMCM_TOUTDUTY

MMCM output clock duty-cycle precision.(4)

0.20

0.20

0.20

ns

MMCM_TLOCKMAX

MMCM maximum lock time.

100.00

100.00

100.00

µs

MMCM_FOUTMAX

MMCM maximum output frequency.

800.00

800.00

800.00

MHz

MMCM_FOUTMIN

MMCM minimum output frequency.(5)(6)

4.69

4.69

4.69

MHz

MMCM_TEXTFDVAR

External clock feedback variation.

< 20% of clock input period or 1 ns Max

MMCM_RSTMINPULSE

Minimum reset pulse width.

5.00

5.00

5.00

ns

MMCM_FPFDMAX

Maximum frequency at the phase frequency detector.

500.00

450.00

450.00

MHz

MMCM_FPFDMIN

Minimum frequency at the phase frequency detector.

10.00

10.00

10.00

MHz

MMCM_TFBDELAY

Maximum delay in the feedback path.

3 ns Max or one CLKIN cycle

MMCM Switching Characteristics Setup and Hold

TMMCMDCK_PSEN/ TMMCMCKD_PSEN

Setup and hold of phase-shift enable.

1.04/0.00

1.04/0.00

1.04/0.00

ns

TMMCMDCK_PSINCDEC/ TMMCMCKD_PSINCDEC

Setup and hold of phase-shift increment/decrement.

1.04/0.00

1.04/0.00

1.04/0.00

ns

TMMCMCKO_PSDONE

Phase shift clock-to-out of PSDONE.

0.68

0.81

0.81

ns

Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK

TMMCMDCK_DADDR/ TMMCMCKD_DADDR

DADDR setup/hold.

1.40/0.15

1.63/0.15

1.63/0.15

ns, Min

TMMCMDCK_DI/ TMMCMCKD_DI

DI setup/hold.

1.40/0.15

1.63/0.15

1.63/0.15

ns, Min

TMMCMDCK_DEN/ TMMCMCKD_DEN

DEN setup/hold.

1.97/0.00

2.29/0.00

2.29/0.00

ns, Min

TMMCMDCK_DWE/ TMMCMCKD_DWE

DWE setup/hold.

1.40/0.15

1.63/0.15

1.63/0.15

ns, Min

TMMCMCKO_DRDY

CLK to out of DRDY.

0.72

0.99

0.99

ns, Max

FDCK

DCLK frequency.

200.00

200.00

200.00

MHz, Max

Notes:

1.The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.

2.The static offset is measured between any MMCM outputs with identical phase.

3.Values for this parameter are available in the Clocking Wizard [Ref 8].

4.Includes global clock buffer.

5.Calculated as FVCO/128 assuming output duty cycle is 50%.

6.When CLKOUT4_CASCADE = TRUE, MMCM_FOUTMIN is 0.036 MHz.