Clock Buffers and Networks

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS189)

Document ID
DS189
Release Date
2022-10-31
Revision
1.10 English
Table  32:   Global Clock Switching Characteristics (Including BUFGCTRL)

Symbol

Description

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

TBCCCK_CE/TBCCKC_CE(1)

CE pins setup/hold.

0.13/0.40

0.16/0.41

0.16/0.41

ns

TBCCCK_S/ TBCCKC_S(1)

S pins setup/hold.

0.13/0.40

0.16/0.41

0.16/0.41

ns

TBCCKO_O(2)

BUFGCTRL delay from I0/I1 to O.

0.09

0.10

0.10

ns

Maximum Frequency

FMAX_BUFG

Global clock tree (BUFG).

628.00

464.00

464.00

MHz

Notes:

1.TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks.

2.TBGCKO_O (BUFG delay from I0 to O) values are the same as TBCCKO_O values.

Table  33:   Input/Output Clock Switching Characteristics (BUFIO)

Symbol

Description

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

TBIOCKO_O

Clock to out delay from I to O.

1.26

1.54

1.54

ns

Maximum Frequency

FMAX_BUFIO

I/O clock tree (BUFIO).

680.00

600.00

600.00

MHz

Table  34:   Regional Clock Buffer Switching Characteristics (BUFR)

Symbol

Description

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

TBRCKO_O

Clock to out delay from I to O.

0.76

0.99

0.99

ns

TBRCKO_O_BYP

Clock to out delay from I to O with Divide Bypass attribute set.

0.39

0.52

0.52

ns

TBRDO_O

Propagation delay from CLR to O.

0.85

1.09

1.09

ns

Maximum Frequency

FMAX_BUFR(1)

Regional clock tree (BUFR).

375.00

315.00

315.00

MHz

Notes:

1.The maximum input frequency to the BUFR is the BUFIO FMAX frequency.

Table  35:   Horizontal Clock Buffer Switching Characteristics (BUFH)

Symbol

Description

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

TBHCKO_O

BUFH delay from I to O.

0.11

0.13

0.13

ns

TBHCCK_CE/ TBHCKC_CE

CE pin setup and hold.

0.22/0.15

0.28/0.21

0.28/0.21

ns

Maximum Frequency

FMAX_BUFH

Horizontal clock buffer (BUFH).

628.00

464.00

464.00

MHz

Table  36:   Duty Cycle Distortion and Clock-Tree Skew

Symbol

Description

Device

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

TDCD_CLK

Global clock tree duty-cycle distortion.(1)

All

0.20

0.20

0.20

ns

TCKSKEW

Global clock tree skew.(2)

XC7S6

0.05

0.06

0.06

ns

XC7S15

0.05

0.06

0.06

ns

XC7S25

0.26

0.26

0.26

ns

XC7S50

0.26

0.26

0.26

ns

XC7S75

0.33

0.36

0.36

ns

XC7S100

0.33

0.36

0.36

ns

XA7S6

0.05

0.06

N/A

ns

XA7S15

0.05

0.06

N/A

ns

XA7S25

0.26

0.26

N/A

ns

XA7S50

0.26

0.26

N/A

ns

XA7S75

0.33

0.36

N/A

ns

XA7S100

0.33

0.36

N/A

ns

TDCD_BUFIO

I/O clock tree duty cycle distortion.

All

0.14

0.14

0.14

ns

TBUFIOSKEW

I/O clock tree skew across one clock region.

All

0.03

0.03

0.03

ns

TDCD_BUFR

Regional clock tree duty cycle distortion.

All

0.18

0.18

0.18

ns

Notes:

1.These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.

2.The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx timing analysis tools to evaluate clock skew specific to your application.