PLL Switching Characteristics

Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS189)

Document ID
DS189
Release Date
2022-10-31
Revision
1.10 English
Table  38:   PLL Specification

Symbol

Description

VCCINT Operating Voltage and Speed Grade

Units

1.0V

0.95V

-2

-1

-1L

PLL_FINMAX

Maximum input clock frequency.

800.00

800.00

800.00

MHz

PLL_FINMIN

Minimum input clock frequency.

19.00

19.00

19.00

MHz

PLL_FINJITTER

Maximum input clock period jitter.

< 20% of clock input period or 1 ns Max

PLL_FINDUTY

Allowable input duty cycle: 19—49 MHz.

25

25

25

%

Allowable input duty cycle: 50—199 MHz.

30

30

30

%

Allowable input duty cycle: 200—399 MHz.

35

35

35

%

Allowable input duty cycle: 400—499 MHz.

40

40

40

%

Allowable input duty cycle: >500 MHz.

45

45

45

%

PLL_FVCOMIN

Minimum PLL VCO frequency.

800.00

800.00

800.00

MHz

PLL_FVCOMAX

Maximum PLL VCO frequency.

1866.00

1600.00

1600.00

MHz

PLL_FBANDWIDTH

Low PLL bandwidth at typical.

1.00

1.00

1.00

MHz

High PLL bandwidth at typical.(1)

4.00

4.00

4.00

MHz

PLL_TSTATPHAOFFSET

Static phase offset of the PLL outputs.(2)

0.12

0.12

0.12

ns

PLL_TOUTJITTER

PLL output jitter.

Note 3

PLL_TOUTDUTY

PLL output clock duty-cycle precision.(4)

0.20

0.20

0.20

ns

PLL_TLOCKMAX

PLL maximum lock time.

100.00

100.00

100.00

µs

PLL_FOUTMAX

PLL maximum output frequency.

800.00

800.00

800.00

MHz

PLL_FOUTMIN

PLL minimum output frequency.(5)

6.25

6.25

6.25

MHz

PLL_TEXTFDVAR

External clock feedback variation.

< 20% of clock input period or 1 ns Max

PLL_RSTMINPULSE

Minimum reset pulse width.

5.00

5.00

5.00

ns

PLL_FPFDMAX

Maximum frequency at the phase frequency detector.

500.00

450.00

450.00

MHz

PLL_FPFDMIN

Minimum frequency at the phase frequency detector.

19.00

19.00

19.00

MHz

PLL_TFBDELAY

Maximum delay in the feedback path.

3 ns Max or one CLKIN cycle

Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK

TPLLDCK_DADDR/ TPLLCKD_DADDR

Setup and hold of D address.

1.40/0.15

1.63/0.15

1.63/0.15

ns, Min

TPLLDCK_DI/ TPLLCKD_DI

Setup and hold of D input.

1.40/0.15

1.63/0.15

1.63/0.15

ns, Min

TPLLDCK_DEN/ TPLLCKD_DEN

Setup and hold of D enable.

1.97/0.00

2.29/0.00

2.29/0.00

ns, Min

TPLLDCK_DWE/ TPLLCKD_DWE

Setup and hold of D write enable.

1.40/0.15

1.63/0.15

1.63/0.15

ns, Min

TPLLCKO_DRDY

CLK to out of DRDY.

0.72

0.99

0.99

ns, Max

FDCK

DCLK frequency.

200.00

200.00

200.00

MHz, Max

Notes:

1.The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.

2.The static offset is measured between any PLL outputs with identical phase.

3.Values for this parameter are available in the Clocking Wizard [Ref 8].

4.Includes global clock buffer.

5.Calculated as FVCO/128 assuming output duty cycle is 50%.