Xil_L1DCacheFlushRange - 2021.1 English

Xilinx Standalone Library Documentation OS and Libraries Document Collection (UG643)

Document ID
UG643
Release Date
2021-06-16
Version
2021.1 English

Flush the level 1 Data cache for the given address range.

If the bytes specified by the address range are cached by the Data cache, the cacheline containing those bytes are invalidated. If the cachelines are modified (dirty), they are written to system memory before the lines are invalidated.

Prototype

void Xil_L1DCacheFlushRange(u32 adr, u32 len);

Parameters

The following table lists the Xil_L1DCacheFlushRange function arguments.

Table 1. Xil_L1DCacheFlushRange Arguments
Name Description
adr 32bit start address of the range to be flushed.
len Length of the range to be flushed in bytes.

Returns

None.