Xil_L1ICacheInvalidateLine - 2021.1 English

Xilinx Standalone Library Documentation OS and Libraries Document Collection (UG643)

Document ID
UG643
Release Date
2021-06-16
Version
2021.1 English

Invalidate a level 1 instruction cache line.

If the instruction specified by the address is cached by the instruction cache, the cacheline containing that instruction is invalidated.

Note: The bottom 5 bits are set to 0, forced by architecture.

Prototype

void Xil_L1ICacheInvalidateLine(u32 adr);

Parameters

The following table lists the Xil_L1ICacheInvalidateLine function arguments.

Table 1. Xil_L1ICacheInvalidateLine Arguments
Name Description
adr 32bit address of the instruction to be invalidated.

Returns

None.