The AI Engine has two 32-bit input
AXI4-Stream interfaces and two 32-bit output
AXI4-Stream interfaces. Each stream is connected
to a FIFO both on the input and output side, allowing the AI Engine to have a four word (128-bit) access per four cycles, or a one
word (32-bit) access per cycle on a stream. A fifo_depth() constraint specification below 40 allocates FIFOs from the
stream switch. The following is an example of a FIFO allocation on the stream switch
requesting a fifo_depth(8).
Figure 1. FIFO Allocation on Stream Switch
