AXI4 I/O Compliant Interfaces - 3.2 English

Following are the AMBA® AXI4 compliant interfaces:

• Two PS General Purpose Master interfaces user configurable as 32, 64, and 128 bits in width. The default width is 128.
• Three PL General Purpose Master interfaces user configurable as 32, 64, and 128 bits in width. The default width is 128.
• A 128-bit PL Master AXI coherency extension (ACE) interface for coherent I/O to CCI module.
• A 128-bit PL Master ACP interface to support L2 cache allocation from PL masters. Limited to 64-byte cache line transfers.

Figure 1. PL-PS Interfaces

The CIPS IP core has two master ports to PL and three slave ports from the PL. Adding to that we have one ACE and one ACP port from the PL. All of them have a maximum default data width of 128 bits and can be selectable as 32-bit, 64-bit, or 128-bit.

The following are the details of the PL interfaces:

ACE

A full ACE slave port (S_ACE_FPD) allowing 2-way coherency between the APU and a PL master. The PL masters can also snoop APU caches via APU ACP port.

ACP

A 1-way coherency slave port (S_ACP_FPD) directly connected the APU, allowing external PL master to allocate memory directly into the L2 cache.

AXI Slave Ports

• Two AXI slave ports (S_AXI_FPD, S_AXI_GP2/S_CCI_FPD) allowing PL masters direct access to the PS not via the NoC
  • PL Masters connected to S_AXI_FPD have access to the following:
    • Complete PS subsystem
    • DDR, PL slaves which are connected to CIPS NCI port
    • PL slaves which are connected to M_AXI_FPD port
  • PL Masters connected to GP2 port have access to the following:
    • Complete PS subsystem
    • DDR, PL slaves which are connected to CIPS CCI port
    • PL slaves which are connected to M_AXI_FPD port
• One direct AXI slave port ( S_AXI_LPD) allowing PL masters access to LPD independent of FPD power state. PL masters connected to this masters has access to complete LPD subsystem.

Note: The GP2 port can be used as either an AXI4 port or as an ACE_Lite port. To enable ACE_Lite mode, enable the GP2 port in the GUI and select the ACE_Lite mode.

AXI Master Ports

• One AXI master port (M_AXI_FPD) allowing PS masters and PL masters (which are connected to CIPS S_AXI_FPD, GP2 and CIPS NOC slave ports) access to PL slaves.
• One direct AXI master port (M_AXI_LPD) allowing LPD masters access to PL slaves independent of FPD power state.

The Versal CIPS IP core provides four resets to the PL. It enables the configuration of these resets to be used in the PL, which are asynchronous to any clock. These resets will be de-asserted after the PL configuration process.

Using this page, you can also configure the PS to PL interface signals related to Ethernet (FIFO, PTP and TSU) and LPD_DMA flow control support.

Masters have to choose different addresses for the connected PL slaves. Based on which AXI port the slaves are connected to CIPS, following table shows the possible addresses for PL slaves.