Port Descriptions - 1.0 English

The following table provides a description of the Embedded Memory Generator core ports. You can select the widths of the data ports (dina, douta, dinb, and doutb) in the AMD Vivado™ IDE. The address port (addrb) widths are determined by the memory depth with respect to each port. The write enable ports (wea and web) are buses (of width one) when byte-writes are disabled. When byte-writes are enabled, wea and web widths depend on the byte size and write data widths selected in Vivado IDE.

Table 1. Core Port Pinout
Port Name	I/O	Port	Description
clka	Input	Port A Clock	Port A operations are synchronous to this clock. For synchronous operation, this must be driven by the same signal as CLKB.
addra	Input	Port A Address	Addresses the memory space for port A Read and Write operations. Available in all configurations.
dina	Input	Port A Data Input:	Data input to be written into the memory through port A. Available in all RAM configurations.
douta	Output	Port A Data Output	Data output from Read operations through port A. Available in all configurations except Simple Dual-port RAM.
ena	Input	Port A Clock Enable	Enables Read, Write, and reset operations through port A. Optional in all configurations.
wea	Input	Port A Write Enable	Enables Write operations through port A. Available in all RAM configurations.
rsta	Input	Port A Set/Reset	Resets the Port A memory output latch or output register. Optional in all configurations.
regcea	Input	Port A Register Enable	Enables the last output register of port A. Optional in all configurations with port A output registers.
sbiterra	Output	Single-Bit Error	Single-bit error in memory which has been auto corrected on the output bus.
dbiterra	Output	Double-Bit Error	Flags the presence of a double-bit error in memory. Double-bit errors cannot be auto-corrected by the built-in ECC decode module.
injectsbiterra	Input	Inject Single-Bit Error	Injects single-bit error to a specific location during Write operation. For more details, see Error Injection.
injectdbiterra	Input	Inject Double-Bit Error	Injects double-bit error to a specific location during Write operation. For more details, see Error Injection.
clkb	Input	Port B Clock	Port B operations are synchronous to this clock. Available in dual-port configurations. For synchronous operation, this must be driven by the same signal as CLKA.
addrb	Input	Port B address	Addresses the memory space for port B Read and Write operations. Available in dual-port configurations.
dinb	Input	Port B Data Input	Data input to be written into the memory through port B. Available in True Dual-port RAM configurations.
doutb	Output	Port B Data Output	Data output from Read operations through Port B. Available in dual-port configurations.
enb	Input	Port B Clock Enable	Enables Read, Write, and reset operations through Port B. Optional in dual-port configurations.
web	Input	Port B Write Enable	Enables Write operations through Port B. Available in Dual-port RAM configurations.
rstb	Input	Port B Set/Reset	Resets the Port B memory output latch or output register. Optional in all configurations.
regceb	Input	Port B Register Enable	Enables the last output register of port B. Optional in dual-port configurations with port B output registers.
sbiterrb	Output	Single-Bit Error	Flags the presence of a single-bit error in memory which has been auto-corrected on the output bus.
dbiterrb	Output	Double-Bit Error	Flags the presence of a double-bit error in memory. Double-bit errors cannot be auto-corrected by the built-in ECC decode module.
injectsbiterrb	Input	Inject Single-Bit Error	Injects single-bit error to a specific location during Write operation. For more details, see Error Injection.
injectdbiterrb	Input	Inject Double-Bit Error	Injects double-bit error to a specific location during Write operation. For more details, see Error Injection.
sleep	Input	Dynamic Power Saving	If sleep pin is High, the Embedded Memory Generator core is in power saving mode.