The combination of the enable
(en
), reset (rst), and register enable (REGCE) pins
allow a wide range of data flows in the output stage. The following figures are examples
on how this can be accomplished. Keep in mind that the rst and REGCE pins apply only to the last
register stage.
The following figure depicts how rst can
be used to control the data output to allow only intended data through. Assume that both
output registers are used for port A, the port A reset value is 0xFFFF, and that en and regce are always
asserted. The data on the memory is labeled LATCH, while the output of the BRAM/URAM
primitive register is labeled REG1. The output of the last register is the output of the
core, dout.
The following figure depicts how REGCE
can be used to latch the data output to allow only intended data through. Assume that
only the memory primitive registers are used for port A, and that en is always asserted and rst is always deasserted. The data on the block RAM memory latch is
labeled latch, while the output of the last register, the block RAM embedded register,
is the core output, dout.
Read Data and Read Enable Latency
The following figure shows the read data (LATCH) and read enable (en) latency
when there are no output registers are used is shown below. The LATCH signal is the data at the output of the
primitive.
The following figure shows the read data (REG1) and read enable (en) latency
when the primitive output register is used. REG1 is
the data at the output of the primitive output register.
The following figure shows the read data (REG2, REG3) and read enable (en) latency when two pipeline stages are used along
with the primitive output register. REG2 is the
data at the output of the pipeline stage 1, and REG3 is the data at the output of the pipeline stage 2.
The following figure shows the read data (dout) and read enable (en) latency
when the core output registers are used along with the primitive output register and
two pipeline stages. dout is the data at the output
of the core output register.
Reset Behavior
The Embedded Memory Generator core provides the reset to output stages of the Memory.
The following figure illustrates the reset behavior in the Embedded Memory Generator. Here, reset is not dependent on enable and both reset operations occur successfully.
