Global Interrupt Enable Register - 5.3 English

MIPI CSI-2 Receiver Subsystem Product Guide (PG232)

Document ID
PG232
Release Date
2023-05-16
Version
5.3 English

The Global Interrupt Enable register is described in Table: Global Interrupt Enable Register (0x20) .

Table 2-11: Global Interrupt Enable Register (0x20)

Bits

Name

Reset Value

Access

Description

31–1

Reserved

N/A

N/A

Reserved

0

Global Interrupt enable

0x0

R/W

Master enable for the device interrupt output to the system

1: Enabled—the corresponding Interrupt Enable register (IER) bits are used to generate interrupts

0: Disabled—Interrupt generation blocked irrespective of IER bits