Core Configuration Register - 5.3 English

31–2

Reserved

N/A

N/A

Reserved

1

Soft Reset

0x0

R/W

1: Resets the core

0: Takes core out of soft reset

All registers reset to their default value except the following:

• Soft Reset bit (offset 0x00 bit[1])

• Core Enable bit (offset 0x00 bit[0])

• Active Lanes Configuration bit (offset 0x04 bit[1:0])

• Global Interrupt Enable Register (offset 0x20)

• Interrupt Enable Register (offset 0x28)

In addition to resetting registers when this bit is set to 1:

• Shut down port is not asserted on the PPI lanes

• Internal FIFOs (PPI, Packet, Generic Short Packet) are flushed

• Control Finite State Machine (FSM) stops processing current packet. Any partially written packet to memory is marked as errored. This packet, when made available through the AXI4-Stream interface, reports the error on TUSER[1].

0

Core Enable

0x1

R/W

1: Enables the core to receive and process packets

0: Disables the core for operation

When disabled:

• Shuts down port assertion on the PPI lanes

• Internal FIFOs (PPI, Packet, Generic Short Packet) are flushed

• Control FSM stops processing current packet
Any partially written packet to memory is marked as errored. This packet, when made available through the AXI4-Stream interface, reports the error on TUSER[1].

Notes:

1. The short packet and line buffer FIFO full conditions take a few clocks to reflect in the register clock domain from the core clock domain due to Clock Domain Crossing (CDC) blocks.