The MIPI CSI-2 RX Controller core latency is the time from the active hs assertion on the PPI interface to valid signal assertion on the controller output.
Table: MIPI CSI-2 RX Controller Latency
provides the latency numbers for various core configurations.
Table 2-2:
MIPI CSI-2 RX Controller Latency
|
Data Type
|
Pixel Mode
|
Line Rate
|
Latency in rxbyteclk
|
Latency in Video Clock
|
|
RAW20
|
Single
|
1000
|
25
|
60
|
|
RAW8
|
Single
|
1000
|
21
|
49
|
|
RAW8
|
Dual
|
1000
|
21
|
49
|
|
RAW8
|
Quad
|
1000
|
21
|
49
|
|
RAW10
|
Single
|
1000
|
25
|
60
|
|
RAW10
|
Dual
|
1200
|
26
|
63
|
|
RAW10
|
Quad
|
800
|
24
|
56
|
|
YUV 422-8Bit
|
Quad
|
2000
|
31
|
18
|
|
Notes:
1.
All the calculations are made for a single lane design with a fixed video clock of 148 MHz.
|