IP Facts - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

Document ID
PG252
Release Date
2023-05-16
Version
2023.1 English
AMD LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 AMD Zynq™ UltraScale+™ MPSoC EV Devices
Supported User Interfaces AXI4
Resources See Resource Utilization
Provided with Core
Design Files RTL
Example Design Not Provided
Test Bench Not Provided
Constraints File Xilinx Constraints File (XDC)
Simulation Model Not Provided
Supported S/W Driver N/A
Tested Design Flows 2
Design Entry AMD Vivado™ Design Suite
Simulation 3 For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
Synthesis Vivado Design Suite
Support
Release Notes and Known Issues Master Answer Record: 66763
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Support web page
  1. For a complete list of supported devices, see the AMD Vivado™ IP catalog.
  2. For the supported versions of the tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
  3. Behavioral simulations using only Verilog simulation models are supported. Netlist (post-synthesis and post-implementation) simulations are not supported.