Software Flow Overview - 2023.1 English

H.264/H.265 Video Codec Unit v1.2 Solutions LogiCORE IP Product Guide (PG252)

Document ID
PG252
Release Date
2023-05-16
Version
2023.1 English

The following diagrams show block designs for encoder/decoder separation, multi-stream (2-stream) Xilinx low-latency mode, and single-stream Xilinx low-latency mode.

Figure 1. Multi-Stream (2-Stream) Xilinx Low Latency

Figure 2. Single-Stream Xilinx Low Latency