| Facts Table | |
|---|---|
| Subsystem Specifics | |
| Supported Device Family 1 |
Versal™ ™ ACAP Zynq® UltraScale+™ RFSoC Zynq® UltraScale+™ MPSoC Virtex® UltraScale+™ Kintex® UltraScale+™ Virtex® UltraScale™ ™ Kintex UltraScale |
| Supported User Interfaces |
AXI4-Stream and AXI4-Lite for all variants
XGMII and GMII for PCS-only variants |
| Resources | Performance and Resource Utilization web page |
| Provided with Subsystem | |
| Design Files | Encrypted register transfer level (RTL) |
| Example Design | Verilog |
| Test Bench | Verilog |
| Constraints File | Xilinx Design Constraints (XDC) |
| Simulation Model | Verilog |
| Supported S/W Driver | N/A |
| Tested Design Flows 2 | |
| Design Entry | Vivado Design Suite |
| Simulation | For supported simulators, see the Xilinx Design Tools: Release Notes Guide. |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 72695 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Xilinx Support web page | |
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