- Gen1 (2.5 GT/s), Gen2 (5.0 GT/s), Gen3 (8.0 GT/s), and Gen4 (16 GT/s) speeds are supported.
- UltraScale devices support 2.5 GT/s, 5.0 GT/s, and 8.0 GT/s line rates with x1, x2, x4, x8 lane operation.
- UltraScale+ devices support 2.5 GT/s, 5.0 GT/s, and 8.0 GT/s line rates with x1, x2, x4, x8, x16 lane operation. Additionally, they support 16.0 GT/s line rate with x1, x2, x4, x8 lane operation.
- Supports P0s low power state when configured as Gen1 or Gen2 only.
- Supports synchronous and asynchronous applications.
- Rate change between Gen1 and Gen2 is a fixed datapath implementation.
- Rate change between Gen3 and Gen4 is a fixed PCLK implementation.
- Low latency enabled by bypassing TX buffer.
- Equalization sequence is part of the GT Quad in Versal devices provided Xilinx MAC is used. For any third party MAC still the equalization is part of the PHY IP.