The GT Selection tab contains the GT selection information. Once the Lane 0 GT Quad and Lane 0 GT Location is selected, then the rest of the GT locations are derived from those two selections. The reference clock selection is also narrowed by the Lane 0 GT Quad and Channel locations. For more information on the GT quad selections, see the UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).
Figure 1. GT Selection Tab for the Core
- Transceiver Type
- Transceiver type allows you to select the type of the transceiver based on
the FPGA selection. Following table shows the transceiver selection available for the IP
core.
Table 1. Transceiver Type Selection Device Transceiver Type VU3P/VU9P GTY ZU9EG GTH KU040 GTH VU440 GTH KU115 GTH - Lane 0 GT Bank
- Selects the GT Quad for lane 0 (Master lane) in the design.
- Lane 0 GT Location
- Once the Lane 0 GT bank is selected, select the Lane 0 GT location under this option. The remainder of the GT locations will be assigned from this location.
- Reference Clock
- Specifies the PCIe reference clock pin for the PCIe MAC GT Selection.