NVMe I/O and Admin Commands Data Flow - 2.0 English

NVMe Target Controller LogiCORE IP Product Guide (PG329)

Document ID
PG329
Release Date
2020-12-04
Version
2.0 English

NVMe Admin Command Flow with C2H Data Transfer

The following figure shows the NVMe admin command flow with C2H data transfer.

Figure 1. Admin Command Flow with C2H Data Transfer

The process is described in the following steps:

  • The host writes the SQ Doorbell through the host_s_axi_lite interface.
  • The NVMe TC IP issues an SQE Fetch request to read 64B SQE from the host.
  • Fetch further PRP lists, if required.
  • Validate the SQE and push to firmware.
  • Firmware issues the WQE Request for WRITE.
  • The NVMe TC IP programs the C2H Descriptor Bypass Out interface, reads data from DDR, and pushes to the C2H Data AXIS Interface.
  • The NVMe TC IP pushes the WQE Completion to firmware.
  • The firmware issues a WQE Completion Request.
  • The NVMe TC IP sends 16B Completion Queue Entry (CQE) to the host and interrupt host.

NVMe I/O Write Command Flow (H2C Data Transfer)

The following figure shows the NVMe I/O write command flow (H2C data transfer).

Figure 2. NVMe WRITE Data Flow

The process is described in the following steps:

  • The host writes the SQ Doorbell through the host_s_axi_lite interface.
  • The NVMe TC IP issues an SQE Fetch request to read 64B SQE from the host.
  • Fetch further PRP lists, if required.
  • Validate the SQE and push to the hardware application.
  • The hardware application issues a WQE Request for READ.
  • The NVMe TC IP programs the H2C Descriptor Bypass Out interface, reads data from DDR, and pushes it to the H2C Data AXIS Interface.
  • The NVMe TC IP pushes the WQE Completion to the hardware application.
  • The hardware application issues the WQE Completion Request.
  • The NVMe TC IP sends 16B Completion Queue Entry (CQE) to the host and interrupt host.

NVMe I/O Read Command Flow (C2H Data Transfer)

The following figure shows the NVMe I/O read command flow (C2H data transfer).

Figure 3. NVMe Read Data Flow

The process is described in the following steps:

  • The host writes the SQ Doorbell through the host_s_axi_lite interface.
  • The NVMe TC IP issues a SQE Fetch request to read 64B SQE from the host.
  • Fetch further PRP lists, if required.
  • Validate the SQE and push to the hardware application.
  • The hardware application issues the WQE Request for WRITE.
  • The NVMe TC IP programs the C2H Descriptor Bypass Out interface, reads data from DDR, and pushes it to the C2H Data AXIS Interface.
  • The NVMe TC IP pushes the WQE Completion to the hardware application.
  • The hardware application issues the WQE Completion Request.
  • The NVMe TC IP sends 16B Completion Queue Entry (CQE) to the host and interrupt host.