The Video Timing Controller can generate up to six output video signals: vertical blank, vertical synchronization, horizontal blank, horizontal synchronization, active video and active chroma. To enable generation of these signals, the Enable Generation GUI parameter must be set, and the control register bit 0 or bit 2 must also be set. Other GUI parameters can be set to selectively disable generation of one or more video timing signals.
The polarity of each output signal can be set by bits 0-5 of the Generator Polarity Register (Address Offset 0x006C). High denotes active-High polarity, and Low denotes active-Low polarity. Bits 8 and 9 of the Control Register also sets the number of lines skipped between each active chroma line. Bit 8 High denotes that every other line is skipped (4:2:0), and Low denotes that no lines are skipped (4:4:4 or 4:2:2). Bit 9 High denotes that every other pixel is skipped, and Low denotes that no pixels are skipped.
The Video Timing Controller has bits in the Control Register called Source Selects to select the internal detection registers or the external input generation registers. These bits allow the detected timing (if enabled) to control the generated outputs or allow the host processor to override each value independently via the generation registers at address offset 0x0060 - 0x0084, as described in Table: AXI4-Lite Address Map .
Table: Example Horizontal Generation Register Inputs through Table: Example Horizontal Generation Register Inputs show example settings of the input control buses and the resultant video timing output signals.
Setting VBLANK to deassert at the same time as HBLANK on the last line of the frame is not supported. The typical use case is for VBLANK to deassert at the same time HBLANK asserts. However, the closest possible configuration to this is off by 1 clock cycle. You can configure VBLANK to deassert one clock cycle before HBLANK deasserts on the last line of the frame. Do this by setting the VBLANK end:
(F0_VBLANK_HEND) = HFRAME_SIZE - 1