XPm_DevIoctl EEMI API - 2022.1 English

Versal ACAP System Software Developers Guide (UG1304)
Document ID
UG1304
Release Date
2022-04-21
Version
2022.1 English

The XPm_DevIoctl EEMI API allows a platform management master to perform specific operations to certain devices.

The following table lists the supported operations in Versal ACAP.

Table 1. XPm_DevIoctl Operations
ID Name Description Arguments
Node ID Arg1 Arg2 Arg3 Return Value
0 IOCTL_GET_RPU_OPER_MODE Returns current RPU operating mode NODE_RPU_0

NODE_RPU_1

 - - - Operating mode:

0: LOCKSTEP

1: SPLIT
1 IOCTL_SET_RPU_OPER_MODE Configures RPU operating mode NODE_RPU_0 NODE_RPU_1 Value of operating mode

0: LOCKSTEP

1: SPLIT

 - - -
2 IOCTL_RPU_BOOT_ADDR_CONFIG Configures RPU boot address

NODE_RPU_0

NODE_RPU_1

 Value to set for boot address

0: LOVEC/TCM

1: HIVEC/OCM

 - - -
3 IOCTL_TCM_COMB_CONFIG Configures TCM to be in split mode or combined mode NODE_RPU_0

NODE_RPU_1

 Value to set (Split/Combined)

0: SPLIT

1: COMB

 - - -
4 IOCTL_SET_TAPDELAY_BYPASS Enable/disable tap delay bypass NODE_QSPI Type of tap delay

2: QSPI

 Tapdelay Enable/Disable

0: DISABLE

1: ENABLE

 - -
6 IOCTL_SD_DLL_RESET Resets DLL logic for the SD device NODE_SD_0,

NODE_SD_1

 SD DLL Reset type

0: ASSERT

1: RELEASE

2: PULSE

 - - -
7 IOCTL_SET_SD_TAPDELAY Sets input/output tap delay for the SD device

NODE_SD_0,

NODE_SD_1

 Type of tap delay to set

0: INPUT

1: OUTPUT

 Value to set for the tap delay

 - -
12 IOCTL_WRITE_GGS Writes value to GGS register - GGS register index (0/1/2/3) Register value to be written - -
13 IOCTL_READ_GGS Returns GGS register value - GGS register index (0/1/2/3) - - Register value
14 IOCTL_WRITE_PGGS Writes value to PGGS register - PGGS register index (0/1/2/3) Register value to be written - -
15 IOCTL_READ_PGGS Returns PGGS register value - PGGS register index (0/1/2/3) - - Register value
17 IOCTL_SET_BOOT_HEALTH_STATUS Sets healthy bit value to indicate boot health status to firmware - healthy bit value - - -
19 IOCTL_PROBE_COUNTER_READ Read probe counter register of LPD/FPD FPD/LPD power domain ID

0x4210002U for LPD

0x420C003U for FPD

 Register configuration

- Counter Number (0 to 7 bit)

- Register Type (8 to 15 bit)

0 - LAR_LSR access (Request Type and Counter Number are ignored)

1 - Main Ctl (Counter Number is ignored)

2 - Config Ctl (Counter Number is ignored)

3 - State Period (Counter Number is ignored)

4 - PortSel

5 - Src

6 - Val

- Request Type (16 to 23 bit)

0 - Read Request

1 - Read Response

2 - Write Request

3 - Write Response

4 - LPD Read Request (For LPD only)

5 - LPD Read Response (For LPD only)

6 - LPD Write Request (For LPD only)

7 - LPD Write Response (For LPD only)

 - - Register value
20 IOCTL_PROBE_COUNTER_WRITE Write probe counter register of LPD/FPD FPD/LPD power domain ID

0x4210002U for LPD

0x420C003U for FPD

 Register configuration

- Counter Number (0 to 7 bit)

- Register Type (8 to 15 bit)

0 - LAR_LSR access (Request Type and Counter Number are ignored)

1 - Main Ctl (Counter Number is ignored)

2 - Config Ctl (Counter Number is ignored)

3 - State Period (Counter Number is ignored)

4 - PortSel

5 - Src

- Request Type (16 to 23 bit)

0 - Read Request

1 - Read Response

2 - Write Request

3 - Write Response

4 - LPD Read Request (For LPD only)

5 - LPD Read Response (For LPD only)

6 - LPD Write Request (For LPD only)

7 - LPD Write Response (For LPD only)

 Register value to be written - -
21 IOCTL_OSPI_MUX_SELECT Select OSPI AXI Multiplexer NODE_OSPI Operation mode

0: Select DMA

1: Select Linear

2: Get mode

 - - Get mode

0: DMA

1: Linear
22 IOCTL_USB_SET_STATE Set USB controller in different device power states NODE_USB_0 Requested power state

0: D0

1: D1

2: D2

3: D3

 - - -
23 IOCTL_GET_LAST_RESET_REASON Get last reset reason of system - - - -

0 – The POR button was pressed outside of the system

1 – An internal POR was caused by software

2 - One of the other SSIT slices caused a POR

3 - An error caused a POR

7 - JTAG TAP initiated system reset

8 - Error initiated system reset

9 - Software initiated system reset

10 - One of the other SSIT slices caused a system reset

15 – Invalid reset reason
24 IOCTL_AIE_ISR_CLEAR Clear AI Engine NPI Interrupts DEV_AIE (0x18224072U) 4-bit NPI Interrupt Clear Mask (wtc)

Bit<3-0> correspond to Interrupt<3-0>

 - - -
28

IOCTL_READ_REG

 Used to securely read a given offset address for a given node ID. - Offset count (=1) - -
29 IOCTL_MASK_WRITE_REG Used to securely write to a given offset address for a given node ID. - Offset mask Value -
33 IOCTL_AIE_OPS AIEML/AIE1 runtime operations for partition init and tear-down. DEV_AIE or Partition node ID (currently unused). Arg1(15:0) : Start column of partition for which wants to run the operation.

Arg1(31:16): Number of columns in partition (or End Column of partition)

 Red value of operation. Here, each bit is related to one operation as below:

Bit value 1 indicate that the operation need to be perform.

 - XST_SUCCESS or Error Code.
34 IOCTL_GET_QOS Get device QoS value - - - - Response returns two values:

0: Default QoS value

1: Current QoS value
Note: IOCTL_GET_QOS currently only supports AI Engine partition nodes for AI Engine clock frequency. The default QoS represents the original boot time divider value and the current QoS value represents the current divider value that is set.
Table 2. Operations
31st to 7th 6th 5th 4th 3rd 2nd 1st 0th
Reserved Set L2 controller NPI INTR Enable AXI4 error events Disable column clock buffer Zeroization of Program and data memories Enable column clock buffer Shim Reset Column Reset