The AXI CDMA core register space is summarized in Table: AXI CDMA Register Summary. The AXI CDMA registers are memory-mapped into non-cacheable memory space.
Note: The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata) signal, and is not impacted by the AXI Write Data Strobe (*_wstrb) signal. For a Write, both the AXI Write Address Valid (*_awvalid) and AXI Write Data Valid (*_wvalid) signals should be asserted together.
IMPORTANT: The registers are 32-bits wide, and the register memory space must be aligned on 128-byte (80h) boundaries.