This register provides the MSB 32 bits of Tail Descriptor Pointer for the AXI CDMA Scatter Gather Descriptor Management. This is applicable only when the address space is greater than 32.
Figure 2-7: TAILDESC_PNTR_MSB Register
|
X-Ref Target - Figure 2-7
|
Table 2-9: TAILDESC_PNTR_MSB Register Details
|
Bits
|
Field Name
|
Default Value
|
Access Type
|
CDMA Mode Used
|
Description
|
|
31 to 0
|
Tail Descriptor Pointer
|
0
|
R/W
(RO)
|
SG
|
Tail Descriptor Pointer. Indicates pause pointer for descriptor chain execution. The AXI CDMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.
When the AXI CDMA is in SG Mode, and the address space is more than 32 bits, (CDMACR.SGMode = 1), a write by the software application to the TAILDESC_PNTR_MSB (in 64 bit mode) register causes the AXI CDMA SG Engine to start fetching descriptors starting from the CURDESC_PNTR register value. If the SG engine is paused at a tail pointer pause point, the SG engine restarts descriptor execution at the next sequential transfer descriptor. If the AXI CDMA is not idle (CDMASR.IDLE = 0), writing to the TAILDESC_PNTR has no effect except to reposition the SG pause point.
This register is cleared when CDMACR.SGMode = 0.
|
|
Notes:
1.RO = Read Only. Writing has no effect.
2.R/W = Read/Write
|
