Features - 4.1 English

AXI Central Direct Memory Access LogiCORE IP Product Guide (PG034)

Document ID

PG034

Release Date

2022-05-18

Version

4.1 English

•AXI4 interface for data transfer

•Independent AXI4-Lite slave interface for register access

•Independent AXI4 Master interface for optional Scatter/Gather function

•Optional Data Realignment Engine

•Register Direct Mode

•Optional Scatter Gather DMA support

•Optional Store and Forward support

•Parameterized Read and Write Address Pipeline depths

•Fixed-address and incrementing-address burst support

LogiCORE IP Facts Table
Core Specifics
Supported Device Family⁽¹⁾	Versal® ACAP UltraScale+™ UltraScale™ Zynq®-7000 SoC, Xilinx 7 series FPGAs
Supported User Interfaces	AXI4, AXI4-Lite
Resources	Performance and Resource Utilization web page
Provided with Core
Design Files	VHDL
Example Design	VHDL
Test Bench	VHDL
Constraints File	Xilinx Design Constraints (XDC) delivered with IP generation
Simulation Model	Not Provided
Supported S/W Driver⁽²⁾	Standalone and Linux
Tested Design Flows⁽³⁾
Design Entry	Vivado Design Suite
Simulation	For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis	Xilinx Synthesis Technology (XST) Vivado Synthesis
Support
Release Notes and Known Issues	Master Answer Record: 54685
All Vivado IP Changes Logs	Master Vivado IP Changes Logs: 72775
Xilinx Support web page
Notes: 1.For a complete list of supported devices, see the Vivado IP catalog. 2.Standalone driver details can be found in the software development kit (SDK) directory. <install_directory>/SDK/<release>/data/embeddedsw/doc/xilinx_drivers.html. Linux OS and driver support information is available from the Xilinx Wiki page. 3.For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.