Using the PLL to Generate the Core Clock - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English

In Virtex-7, Artix-7, and Kintex-7 devices the use_pll input to the example design can be tied to High to enable the core to use a PLLE2 in place of a MMCME2 in the core clock path. This might help with clocking resource utilization in designs containing multiple CPRI cores.

To use the PLLE2 the following changes should be made to the < component_name>_tx_clk_gen.vhd file located in the <project_directory>/example_design/gtx_and_clocks directory.

First, the MMCME2 instance mmcm_adv_inst should be replaced with the following PLLE2_ADV instance:

mmcm_adv_inst: PLLE2_ADV

generic map

(BANDWIDTH            => “HIGH”,

COMPENSATION         => “ZHOLD”,

CLKOUT0_PHASE        => 0.000,

CLKFBOUT_PHASE       => 0.000,

CLKOUT0_DUTY_CYCLE   => 0.50,

CLKIN1_PERIOD        => 8.138,

REF_JITTER1          => 0.010,

-- See table 5-5 for the following parameter settings

DIVCLK_DIVIDE        => 1,

CLKFBOUT_MULT        => 10,

CLKOUT0_DIVIDE       => 8,

CLKOUT1_DIVIDE       => 8,

CLKOUT2_DIVIDE       => 8,

CLKOUT3_DIVIDE       => 8,

CLKOUT4_DIVIDE       => 8,

CLKOUT5_DIVIDE       => 8)

port map

-- Output clocks

(CLKFBOUT            => fb,

CLKOUT0             => clkout0_i,

CLKOUT1             => clkout1_i,

CLKOUT2             => clkout2_i,

CLKOUT3             => clkout3_i,

CLKOUT4             => clkout4_i,

CLKOUT5             => clkout5_i,

-- Input clock control

CLKFBIN             => fb,

CLKIN1              => refclk,

CLKIN2              => '0',

-- Tied to always select the primary input clock

CLKINSEL            => '1',

-- Ports for dynamic reconfiguration

DADDR               => daddr_i(6 downto 0),

DCLK                => dclk,

DEN                 => den_i,

DI                  => di_i,

DO                  => do,

DRDY                => drdy,

DWE                 => dwe_i,

-- Other control and status signals

LOCKED              => clk_ok_i,

PWRDWN              => '0',

RST                 => reset);

The settings for the DIVCLK_DIVIDE, CLKFBOUT_MULT and CLKOUT_DIVIDE parameters are detailed in Table: PLLE2 Parameter Settings . The CLKIN1_PERIOD should also be changed to the period of the reference clock. If the MMCME2 is constrained to a specific location in the XDC constraints file, a suitable PLL location should be substituted.

Table 4-2: PLLE2 Parameter Settings

Reference Clock

DIVCLK_DIVIDE

CLKFBOUT_MULT

CLKOUT_DIVIDE

3,072.0 Mb/s capable cores

122.88 MHz

1

10

8

153.60 MHz

2

16

8

6,144.0 Mb/s capable cores

122.88 MHz

4

40

4 (1)

153.60 MHz

4

32

4 (1)

245.76 MHz

4

20

4 (1)

307.20 MHz

4

16

4 (1)

9,830.4 Mb/s capable cores

122.88 MHz

1

10

5

153.60 MHz

1

8

5

245.76 MHz

2

10

5

307.20 MHz

2

8

5

Notes:

1. Set CLKOUT_DIVIDE to 8 for 32-bit datapath cores.