This section details the CPRI™ core clocking for correct operation at all supported speeds for each device family.
The clocks are generated from the GT transceivers in the block level of the CPRI core. For UltraScale and 7 series cores, when the design is generated without the core support layer, this corresponds to the top level of the core. When the support layer is included in the core, the client clock and the recovered clock (the clk_in and recclk_in inputs to the block level) are output from the core on the clk_out and recclk ports. See CPRI Core Structure for more information on the core support and block layers of the design.