Transceiver Status and Control Interface (Versal ACAP Cores Only) - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English

Table: Versal Transceiver Status and Control Ports shows the Versal transceiver status and control ports.

Table 3-31: Versal Transceiver Status and Control Ports

Port

Direction

Clock Domain

Description

gtpowergood

In

Async

This active-High signal from Versal ACAP. Transceiver indicates when the GT clocking resources have completed power up.

encommaalign

Out

Recovered Clock

This active-High output is used to control the 8b10b comma alignment logic in the Versal ACAP transceiver. Active-High for 8b10b encoding and low for 64b66b encoding.

loopback[2:0]

Out

Management Clock

This signal to the Versal ACAP Transceiver controls the various loopback modes.

Notes:

1. The ports gtpowergood and loopback[2:0] are connected between the CPRI core and the Versal ACAP Transceiver using Block Automation, see Block Automation (Versal ACAP Only) for details.

2. The port encommaalign should be connected to the GT Quad IP GPI[15:0] Interface. If using GT Quad, Ch0 connects to GPI[8], Ch1 connects to GPI[9], Ch2 connects to GPI[10], and Ch3 connects to GPI[11]. For an example of this connection, generate the CPRI example design (see Example Design ).