Transceiver Debug Interface - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English

Note: The Transceiver Debug Interface is not available when using Versal ACAP.

Selecting the Additional Transceiver Control and Status Ports option on the Vivado CPRI core customization screen enables direct access to selected transceiver control and status pins. See the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 4] , UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 5] , the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 2] , and the 7 Series FPGAs GTP Transceivers User Guide (UG482) [Ref 3] for more information on these signals. The transceiver debug pins in Zynq-7000 SoC, Virtex-7, Kintex-7, and Artix-7 cores are described in Table: Transceiver Debug Signals (Zynq-7000 SoC, Virtex-7, Kintex-7 and Artix-7) .

IMPORTANT: The ports in the Transceiver Control And Status Interface must be driven in accordance with the appropriate GT user guide. Using the input signals listed in Table: Transceiver Debug Signals (Zynq-7000 SoC, Virtex-7, Kintex-7 and Artix-7) can result in unpredictable behavior of the IP core.

Table 3-34: Transceiver Debug Signals (Zynq-7000 SoC, Virtex-7, Kintex-7 and Artix-7)

Port Name (1)

Direction

Clock Domain

Description

gt0_drpdaddr_in[8:0]

In

Management Clock

DRP address

gt0_drpdi_in[15:0]

In

Management Clock

DRP write data

gt0_drpen_in

In

Management Clock

DRP Enable

gt0_drpwe_in

In

Management Clock

DRP write enable

gt0_drpdo_out[15:0]

Out

Management Clock

DRP read data

gt0_drprdy_out

Out

Management Clock

DRP ready

gt0_txpmareset_in

In

Async

This port is pulsed High to start the TX PMA reset process.

gt0_txpcsreset_in

In

Async

This port is pulsed High to start the TX PCS reset process.

gt0_txresetdone_out

Out

Async

A High on this port indicates that the TX reset process has completed.

gt0_rxpmareset_in

In

Async

This port is pulsed High to start the RX PMA reset process.

gt0_rxpcsreset_in

In

Async

This port is pulsed High to start the RX PCS reset process.

gt0_rxpmaresetdone_out

Out

Async

(GTHE2 and GTPE2 transceiver based cores only.) A High on this port indicates that the RX PMA reset process has completed.

gt0_rxresetdone_out

Out

Async

A High on this port indicates that the RX reset process has completed.

gt0_txphaligndone_out

Out

Async

A High on this port indicates that TX phase alignment has completed.

gt0_txphinitdone_out

Out

Async

A High on this port indicates that TX phase alignment initialization has completed.

gt0_txdlysresetdone_out

Out

Async

A High on this port indicates that TX delay alignment soft reset has completed.

gt0_rxphaligndone_out

Out

Async

The second rising edge detected on this port after the assertion of gt0_rxdlysresetdone_out indicates that RX phase and delay alignment have completed.

gt0_rxdlysresetdone_out

Out

Async

A High on this port indicates that RX delay alignment soft reset has completed.

gt0_rxsyncdone_out

Out

Async

(GTHE2 and GTPE2 transceiver based cores only.) Indicates that the RX buffer bypass alignment procedure has completed.

gt0_cplllock_out

Out

Async

Active-High signal indicating that the channel PLL has locked to the input reference clock

gt0_qplllock_out

Out

Async

Cores supporting 9,830.4, 10,137.6, and 12,165.12 Mb/s only. Active-High signal indicating that the quad PLL has locked to the input reference clock.

gt0_eyescantrigger_in

In

Recovered Clock

A High on this port causes an EYESCAN trigger event.

gt0_eyescanreset_in

In

Async

This port is pulsed High to initiate the EYESCAN reset process.

gt0_eyescandataerror_out

Out

Async

Asserted when an EYESCAN error occurs.

gt0_rxpolarity_in

In

Recovered Clock

Set High to invert the incoming serial data.

gt0_txpolarity_in

In

System Clock

Set High to invert the outgoing serial data.

gt0_rxdfelpmreset_in

In

Async

(GTXE2 and GTHE2 transceiver based cores only.) Reset for the low power mode (LPM) and decision feedback equalizer (DFE) datapath.

gt0_rxlpmen_in

In

Async

(GTXE2 and GTHE2 transceiver based cores only.) Set to 1 to select the LPM datapath.

gt0_rxlpmreset_in

In

Async

(GTPE2 transceiver based cores only.) This port is pulsed High to initiate the LPM reset process.

gt0_rxlpmhfhold_in

In

Async

(GTPE2 transceiver based cores only.) High frequency boost control

gt0_rxlpmhfovrden_in

In

Async

(GTPE2 transceiver based cores only.) High frequency boost control

gt0_rxlpmlfhold_in

In

Async

(GTPE2 transceiver based cores only.) Low frequency boost control

gt0_txprecursor_in[4:0]

In

Async

Transmitter pre-cursor pre-emphasis control

gt0_txpostcursor_in[4:0]

In

Async

Transmitter post-cursor pre-emphasis control

gt0_txdiffctrl_in[3:0]

In

Async

Driver swing control

gt0_txprbsforceerr_in

In

System Clock

Set High to drive errors into the pseudo-random binary sequence (PRBS) transmitter.

gt0_txprbssel_in[2:0]

In

System Clock

Transmitter PRBS generator test pattern control

gt0_rxprbssel_in[2:0]

In

Recovered Clock

Receiver PRBS checker test pattern control

gt0_rxprbserr_out

Out

Recovered Clock

A High on this port indicates that PRBS errors have occurred.

gt0_rxprbscntreset_in

In

Recovered Clock

Reset the PRBS error counter

gt0_rxcdrhold_in

In

Async

Hold the clock data recovery (CDR) control loop frozen.

gt0_dmonitorout_out

Out

Async

Digital Monitor Output Bus. The bus is 15-bits wide in GTHE2 and GTPE2 transceiver based cores and 8-bits wide in GTXE2 transceiver based cores.

gt0_rxdisperr_out

Out

Recovered Clock

Receiver disparity error indicator. The bus is 2-bits wide in 16-bit datapath cores and 4-bits wide in 32-bit datapath cores.

gt0_rxnotintable_out

Out

Recovered Clock

Receiver not in table error indicator. The bus is 2-bits wide in 16-bit datapath cores and 4-bits wide in 32-bit datapath cores.

gt0_rxcommadet_out

Out

Recovered Clock

A High on this port indicates that the comma alignment block has detected a valid comma.

gt0_rxheader_out

Out

Recovered Clock

(10,137.6 and 12,165.12 Mb/s implementations only) Header output from the transceiver.

gt0_rxheadervalid_out

Out

Recovered Clock

(10,137.6 and 12,165.12 Mb/s implementations only) Header valid output from the transceiver.

Notes:

1. If you are migrating from a 7 series to an UltraScale device, the prefixes of the optional transceiver debug ports are changed from gt0 to gt and the postfix _in and _out are dropped (see Table: Transceiver Debug Signals (UltraScale Architecture) ).

The transceiver debug pins for cores implemented on UltraScale architecture are shown in Table: Transceiver Debug Signals (UltraScale Architecture) .

Table 3-35: Transceiver Debug Signals (UltraScale Architecture)

Port Name

Direction

Clock
Domain

Description

gt_drpdaddr

In

Management
Clock

(GTHE3 transceiver based cores) DRP address width is [8:0]

(GTHE4, GTYE3 and GTYE4 transceiver-based cores) DRP address width is [9:0]

gt_drpdi[15:0]

In

Management
Clock

DRP write data

gt_drpen

In

Management
Clock

DRP Enable

gt_drpwe

In

Management
Clock

DRP write enable

gt_drpdo[15:0]

Out

Management
Clock

DRP read data

gt_drprdy

Out

Management
Clock

DRP ready

gt_txpmareset

In

Async

This port is pulsed High to start the TX PMA reset process.

gt_txpcsreset

In

Async

This port is pulsed High to start the TX PCS reset process.

gt_txresetdone

Out

Async

A High on this port indicates that the TX reset process has completed.

gt_rxpmareset

In

Async

This port is pulsed High to start the RX PMA reset process.

gt_rxpcsreset

In

Async

This port is pulsed High to start the RX PCS reset process.

gt_rxpmaresetdone

Out

Async

A High on this port indicates that the RX PMA reset process has completed.

gt_rxresetdone

Out

Async

A High on this port indicates that the RX reset process has completed.

gt_txphaligndone

Out

Async

A High on this port indicates that TX phase alignment has completed.

gt_txphinitdone

Out

Async

A High on this port indicates that TX phase alignment initialization has completed.

gt_txdlysresetdone

Out

Async

A High on this port indicates that TX delay alignment soft reset has completed.

gt_rxphaligndone

Out

Async

The second rising edge detected on this port after the assertion of gt_rxdlysresetdone_out indicates that RX phase and delay alignment have completed.

gt_rxdlysresetdone

Out

Async

A High on this port indicates that RX delay alignment soft reset has completed.

gt_rxsyncdone

Out

Async

Indicates that the RX buffer bypass alignment procedure has completed.

gt_cplllock

Out

Async

Active-High signal indicating that the channel PLL has locked to the input reference clock.

gt_qplllock

Out

Async

Cores supporting 9,830.4, 10,137.6, 12,165.12, or 24,330.24 Mb/s with shared logic in the core only. Active-High signal indicating that the quad PLL has locked to the input reference clock.

gt_rxrate[2:0]

In

Recovered
Clock

Link signaling rate control

gt_eyescantrigger

In

Recovered
Clock

A High on this port causes an EYESCAN trigger event.

gt_eyescanreset

In

Async

This port is pulsed High to initiate the EYESCAN reset process.

gt_eyescandataerror

Out

Async

Asserted when an EYESCAN error occurs.

gt_rxpolarity

In

Recovered
Clock

Set High to invert the incoming serial data.

gt_txpolarity

In

System Clock

Set High to invert the outgoing serial data.

gt_rxdfelpmreset

In

Async

Reset for the LPM and DFE datapath.

gt_rxlpmen

In

Async

Set to 1 to select the LPM datapath.

gt_txprecursor[4:0]

In

Async

Transmitter pre-cursor pre-emphasis control

gt_txpostcursor[4:0]

In

Async

Transmitter post-cursor pre-emphasis control

gt_txdiffctrl

In

Async

(GTHE3 transceiver based cores) Driver swing control width is [3:0].

(GTYE3, GTHE4 and GTYE4 transceiver-based cores) Driver swing control width is [4:0].

gt_txprbsforceerr

In

System
Clock

Set High to drive errors into the PRBS transmitter.

gt_txprbssel[3:0]

In

System
Clock

Transmitter PRBS generator test pattern control.

gt_rxprbssel[3:0]

In

Recovered
Clock

Receiver PRBS checker test pattern control

gt_rxprbserr

Out

Recovered
Clock

A High on this port indicates that PRBS errors have occurred.

gt_rxprbscntreset

In

Recovered
Clock

Reset the PRBS error counter.

gt_rxcdrhold

In

Async

Hold the CDR control loop frozen.

gt_dmonitorout[14:0]

Out

Async

Digital Monitor Output Bus.

gt_rxdisperr

Out

Recovered
Clock

Receiver disparity error indicator. The bus is 2-bits wide in 16-bit datapath cores and 4-bits wide in 32-bit datapath cores.

gt_rxnotintable

Out

Recovered
Clock

Receiver not in table error indicator. The bus is 2-bits wide in 16-bit datapath cores and 4-bits wide in 32-bit datapath cores.

gt_rxcommadet

Out

Recovered
Clock

A High on this port indicates that the comma alignment block has detected a valid comma.

gt_rxheader

Out

Recovered
Clock

(10137.6, 12,165.12, and 24,330.24 Mb/s implementations only) Header output from the transceiver.

gt_rxheadervalid

Out

Recovered
Clock

(10137.6, 12,165.12, and 24,330.24 Mb/s implementations only) Header valid output from the transceiver.

gt_pcsrsvdin[15:0]

In

Async

(GTHE3/GTYE3 transceiver based cores) Set bit 2 High to reset the DRP.