Bits 31:16 of this register carry read-only information on the version of the core. Bits 15:8 are the latched error register bits and are set High when the relevant error condition is detected. They are reset when register 0x1 is read through the management interface.
|
Bits |
Description |
|---|---|
|
31:24 |
Major version |
|
23:20 |
Minor version |
|
19:16 |
Revision |
|
15 |
Latched version of local loss of frame synchronization (LOF) |
|
14 |
Latched version of local loss of signal (LOS) |
|
13 |
Latched version of local RAI |
|
12 |
Latched version of remote loss of frame synchronization (LOF) |
|
11 |
Latched version of remote loss of signal (LOS) |
|
10 |
Latched version of remote Service Access Point (SAP) Defect Indication |
|
9 |
Latched version of remote RAI |
|
8 |
Latched version of remote Reset |
|
7 |
When 1, core is a master port; when 0, core is a slave port. |
|
6 |
When 1, core has been generated using a hardware evaluation license |
|
5:2 |
Reserved |
|
1 |
Local loss of frame synchronization (1) |
|
0 |
Local loss of signal (1) |
|
Notes: 1. Bits 0 and 1 are not latched and clear by themselves when LOS and LOF clear. |
|