The core support layer contains elements that can be shared between multiple CPRI cores. In this level the following blocks are instantiated.
• Transmit clock logic : In Zynq-7000 SoC-based and 7 series-based designs an mixed-mode clock manager (MMCM) is used to generate the system clock. This is routed to the core layer through a BUFG. A state machine to change the MMCM clock divider settings on a speed change is also included. In UltraScale architecture and Zynq UltraScale MPSoC/RFSoC designs, the clock divider settings are set by the transceiver rather than by an external MMCM. The transmitter output clock from the transceiver is routed to the core layer through a BUFG_GT.
• Receive clock logic : The recovered clock output from the transceiver is routed to the core layer through a clock buffer. In Zynq-7000 SoC-based and 7 series-based designs you can select a BUFH, BUFG or BUFR to implement the receiver clock buffering. In UltraScale and Zynq UltraScale MPSoC and RFSoC architecture designs, a BUFG_GT is used.
• Common Block Wrapper : The transceiver common block GT_COMMON, containing the quad phase-locked loop (QPLL). In Zynq-7000 SoC-based and 7 series-based designs one common block is required for a group of four cores sharing the same quad in the device. In UltraScale and Zynq UltraScale MPSoC and RFSoC architecture designs, the common block wrapper is only present in cores supporting line speeds over 9,830.4 Mb/s.
• Transmit Alignment : With the exception of 64B66B line rates on UltraScale and Zynq UltraScale MPSoC and RFSoC devices, the CPRI core bypasses the transmit and receive buffers. This ensures predictable and measurable latency. In buffer bypass mode, phase and delay alignment must be carried out after a reset or a change in line rate. If the MMCM is shared between multiple cores, transmit phase alignment is implemented in multi-lane manual mode. See the “TX Buffer Bypass” section in the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 2] , the 7 Series FPGAs GTP Transceivers User Guide (UG482) [Ref 3] , the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 4] and the UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 5] for more information. The transmit multi-lane manual mode phase alignment provided by the TX Sync block is carried out in the core support layer as it performs the alignment for multiple transceivers. The CPRI core support layer provides I/O for up to three other CPRI cores to share the transmitter alignment block. When running at 64B66B line rates on UltraScale devices, instead of bypassing the buffer, the asynchronous gearbox is used. The latency across the gearboxes is reported in Gearbox Latency Register (0x16) .
• Reset Generation : A reset block is used to generate the reset to the transceiver common block.
Optionally the CPRI core can be generated without the core support layer. In this case the core top level corresponds to the block layer in This Figure . An example design provided with the core includes the logic provided by the core support layer in This Figure . This Figure shows a block diagram of the core when it is generated without the core support layer.
|
For more information on sharing the resources between multiple cores see Resource Sharing . The core support layer is discussed in more detail in Output Generation .