Connecting the CPRI core to an Ethernet MAC on the FPGA - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English

An example of connecting the CPRI core to the Xilinx Tri-mode Ethernet MAC LogiCORE IP in MII mode is shown in This Figure .

Figure 3-60: Interfacing the Tri-mode Ethernet MAC to the CPRI Core in MII Mode

X-Ref Target - Figure 3-60

ethernet_mii.jpg

The Tri-mode Ethernet MAC core is generated with an internal physical interface and the half duplex option selected. This enables the eth_crs and eth_col flow control method described in the previous section to be used.

The FIFO block level of the Tri-mode Ethernet MAC can also be used in place of the core support layer to provide buffering and frame retransmission at the client interface of the TEMAC.

This Figure shows an example of connecting the CPRI core to the Tri-mode Ethernet MAC in GMII mode.

Figure 3-61: Interfacing the Tri-mode Ethernet MAC to the CPRI Core in GMII Mode

X-Ref Target - Figure 3-61

ethernet_gmii.jpg

The Tri-mode Ethernet MAC core is generated with an internal physical interface and the full duplex option selected. The Ethernet MAC speed is set to 1,000 Mb/s.

The CPRI core does not support GMII half duplex mode as the frame extensions used in the frame bursting at 1,000 Mb/s are not passed across the CPRI link. Therefore the standard CSMA/CD half-duplex collision mechanism cannot be used to provide flow control. Care must be taken to avoid exceeding the maximum Ethernet data rate for the selected CPRI line rate.

The CPRI core can also be connected to an external Ethernet MAC. For more information on how to connect using GMII see Using an External GMII Interface .