The bits in this register define the line speeds that the core should use.
Bits |
Description |
---|---|
31:15 |
Reserved |
14 |
Capable of 24,330.24 Mb/s FEC Enabled Mode (Versal GTY or UltraScale GTYE3/GTYE4 only) |
13 |
Capable of 12,165.12 Mb/s FEC Enabled Mode (Versal GTY or UltraScale GTYE3/GTYE4 only) |
12 |
Capable of 10,137.6 Mb/s FEC Enabled Mode (Versal GTY or UltraScale GTYE3/GTYE4 only) |
11 |
Capable of 8,110.08 Mb/s FEC Enabled Mode (Versal GTY or UltraScale GTYE3/GTYE4 only) |
10 |
Capable of 24,330.24 Mb/s (Versal GTY or UltraScale GTYE3/GTYE4 only) |
9 |
Capable of 12,165.12 Mb/s |
8 |
Capable of 8,110.08 Mb/s |
7 |
Capable of 10,137.6 Mb/s |
6 |
Capable of 9,830.4 Mb/s |
5 |
Capable of 6,144.0 Mb/s |
4 |
Capable of 4,915.2 Mb/s |
3 |
Capable of 3,072.0 Mb/s |
2 |
Capable of 2,457.6 Mb/s |
1 |
Capable of 1,228.8 Mb/s |
0 |
Capable of 614.4 Mb/s |
Notes: 1. Setting 000 0000 0000 0000 disables the core.
2.
In cores that do not support 6,144.0 Mb/s operation, writes to bits 4 through 14 are ignored. In cores that do not support 9,830.4 Mb/s operation, writes to bits 6 through 14 are ignored.
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Table: Line Speed Capability Register Defaults shows the defaults for the Line Speed Capability Register, depending on the speed capability that is selected.