Features - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English

Supports GTY transceivers on Versal adaptive compute acceleration platforms (ACAPs) at line rates of 2,457.6, 3,072, 4,915.2, 6,144, 8,110.08, 9,830.4, 10,137.6, 12,165.12, and 24,330.24 Mb/s.

Supports GTHE3, GTYE3, GTHE4, or GTYE4 transceivers on UltraScale™ devices at line rates of 614.4, 1,228.8, 2,457.6, 3,072, 4,915.2, 6,144, 8,110.08, 9,830.4, 10,137.6, 12,165.12, and 24,330.24 Mb/s.

Optional 100G Ethernet RS-FEC supported using GTYE4 transceivers on selected UltraScale+, RFSoC and MPSoC devices at a fixed line rate of either 24,330.24, 12,165.12, 10,137.6, or 8,110.08 Mb/s.

CPRI core can be converted into a four lane Receiver Hard FEC IP running at a fixed line rate of either 24,330.24, 12,165.12, 10,137.6, or 8,110.08 Mb/s.

Supports GTXE2 or GTHE2 transceivers on Zynq®-7000 SoC, Virtex®-7, and Kintex®-7 devices at line rates of 614.4, 1,228.8, 2,457.6, 3,072, 4,915.2, 6,144, 9,830.4, and 10,137.6 Mb/s.

Supports GTPE2 transceivers on Artix®-7 devices at line rates of 614.4, 1,228.8, 2,457.6, 3,072, 4,915.2, and 6,144 Mb/s.

UTRA-FDD in-phase and quadrature-phase data (I/Q) module supporting 1 to 48 Antenna-Carriers per core.

Automatic speed negotiation.

Supports both Fast (Ethernet) and Slow High-Level Data Link Control (HDLC) Control and Management (C&M) channels per CPRI Specification v7.0 [Ref 1] .

Supports Structure Agnostic Interface at 24,220.24 - 2,457.6 Mb/s line rates.

LogiCORE IP Facts

Core Specifics

Supported
Device Family (1)

Versal ACAP

Zynq ® UltraScale+ MPSoC, RFSoC
UltraScale+
(5)

UltraScale
Zynq-7000 SoC
(2)
7 Series (3)

See Speed Grade Support .

Supported User
Interfaces

Generic data, status, configuration and
management interfaces,

AXI4-Lite management interface

Resources

Performance and Resource Utilization web page

Provided with Core

Design Files

Encrypted register transfer level (RTL)

Example Design

VHDL

Test Bench

VHDL

Constraints File

Xilinx Design Constraints (XDC)

Simulation Models

VHDL, Verilog

Supported
S/W Drivers

N/A

Tested Design Flows (4)

Design Entry

Vivado ® Design Suite

Simulation

For supported simulators, see the
Xilinx Design Tools: Release Notes Guide .

Synthesis

Vivado Synthesis

Support

Release Notes and Known Issues

Master Answer Record: 54473

All Vivado IP Change Logs

Master Vivado IP Change Logs: 72775

Xilinx Support web page

Notes:

1. For a complete list of supported devices, see the Vivado IP catalog.

2. Excludes the Zynq-7000 SoC 007, 010, 014, and 020 devices.

3. Excludes the Artix-7 100T device in CSG324, FTG256, and CS324 packages (Excludes Spartan-7 devices).

4. For the supported versions of third-party tools, see the
Xilinx Design Tools: Release Notes Guide .

5. Excludes Zynq UltraScale+ devices 2cg, 2eg, 3cg, and 3eg.