I/Q Interface - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English

The I/Q interface of the CPRI core gives direct access to the multiplexed and mapped I/Q data stream as it appears on the CPRI link. As such, use of this interface requires detailed knowledge of the CPRI mapping protocol in use by the designer; however, it is an extremely flexible and powerful interface to use for transporting I/Q data.

Three I/Q data adapter modules are also delivered with the core example design: I/Q multiplexers that support the UTRA-FDD and E-UTRA sample mappings described in the CPRI specification and a legacy raw I/Q module to match the raw I/Q interface timing of v1.2 and earlier of the CPRI core.

The ports shown in Table: I/Q Interface Signals are used to pass I/Q data.

Table 3-6: I/Q Interface Signals

Port

Direction

Clock Domain

Description

iq_tx

In

System Clock

Transmit I/Q data. Synchronous to clk. 64 bits wide when the 64-bit datapath option is selected; 32-bits wide when the 32-bit datapath option is selected; 16-bits wide otherwise.

iq_tx_enable

Out

System Clock

Transmit enable indicating the start of a new T c.

iq_rx

Out

System Clock

Receive I/Q data. Synchronous to clk . 64 bits wide when the 64-bit datapath option is selected; 32-bits wide on when the 32-bit datapath option is selected; 16-bits wide otherwise.

basic_frame_first_word

Out

System Clock

Indicates the start of a new basic frame, asserted once every T c.

Figure 3-1: 16-Bit Wide I/Q Transmit Interface at 614.4 Mb/s

X-Ref Target - Figure 3-1

iq_transmit_614.jpg

The signal basic_frame_first_word marks the start of a new basic frame. The signal iq_rx is sampled on the rising edge of clk . A basic frame at 614.4 Mb/s is 16 bytes in length, with the first byte being the control word. The control word, denoted as XX in This Figure is ignored and can be any value. Bytes are sent out in the basic frame in the following order:

XX, 00, 11, 22, 33 …

Similarly for the receive interface at 614.4 Mb/s:

Figure 3-2: 16-Bit Wide IQ Receive Interface at 614.4 Mb/s

X-Ref Target - Figure 3-2

iq_receive_614.jpg

The signal basic_frame_first_word marks the start of a new basic frame. The signal iq_rx is sampled on the rising edge of clk . The control word data, present in the first byte at 614.4 Mb/s should be ignored. Bytes are received in the basic frame in the following order:

cw, 00, 11, 22, 33 …

Other speeds follow a similar format. The length of the basic frame and the control word is expanded. For 1,228.8 Mb/s, the basic frame is 32 bytes in length, and the first two bytes are the control word. For 2,457.6 Mb/s, the basic frame is 64 bytes in length, and the first four bytes are the control word.

For 3,072 Mb/s, the basic frame is 80 bytes in length and the first five bytes are the control word. At 4,915.2 Mb/s the basic frame is 128 bytes in length and the first 8 bytes are the control word. At 6,144.0 Mb/s the basic frame is 160 bytes in length and the first 10 bytes are the control word. Figures 3-2 through 3-12 illustrate the 16-bit wide I/Q Transmit and Receive Interfaces at a range of speeds.

Figure 3-3: I/Q Transmit Interface at 1,228.8 Mb/s

X-Ref Target - Figure 3-3

iq_transmit_1228.jpg
Figure 3-4: I/Q Receive Interface at 1,228.8 Mb/s

X-Ref Target - Figure 3-4

iq_receive_1228.jpg
Figure 3-5: I/Q Transmit Interface at 2,457.6 Mb/s

X-Ref Target - Figure 3-5

iq_transmit_2458.jpg
Figure 3-6: I/Q Receive Interface at 2,457.6 Mb/s

X-Ref Target - Figure 3-6

iq_receive_2457.jpg
Figure 3-7: I/Q Transmit Interface at 3,072.0 Mb/s

X-Ref Target - Figure 3-7

iq_transmit_3072.jpg
Figure 3-8: I/Q Receive Interface at 3,072.0 Mb/s

X-Ref Target - Figure 3-8

iq_receive_3072.jpg
Figure 3-9: I/Q Transmit Interface at 4,915.2 Mb/s

X-Ref Target - Figure 3-9

iq_transmit_4915.jpg
Figure 3-10: I/Q Receive Interface at 4,915.2 Mb/s

X-Ref Target - Figure 3-10

iq_receive_4915.jpg
Figure 3-11: I/Q Transmit Interface at 6,144.0 Mb/s

X-Ref Target - Figure 3-11

iq_transmit_6144.jpg
Figure 3-12: I/Q Receive Interface at 6,144.0 Mb/s

X-Ref Target - Figure 3-12

iq_receive_6144.jpg

When the 32-bit datapath option is selected, the I/Q data bus is widened to 32 bits. The data transfers follow a similar format to the 16-bit I/Q interface; however, 4 bytes of data are input and output on each clock period. The basic frame is 4 clock periods long at 614.4 Mb/s, 8 clock periods at 1,228.8 Mb/s, 16 clock periods at 2,457.6 Mb/s, 20 clock periods at 3,072.0 Mb/s, 32 clock periods at 4,915.2 Mb/s, 40 clock periods at 6,144.0 Mb/s, and 64 clock periods at 8,110.08 Mb/s and 9,830.4 Mb/s. The control word is 16 bytes long at 8,110.08 Mb/s and 9,830.4 Mb/s. This Figure and This Figure illustrate the 32-bit wide I/Q Transmit and Receive Interfaces at 8,110.08 Mb/s and 9,830.4 Mb/s.

Figure 3-13: 32-Bit Wide Transmit Interface at 8,110.08 Mb/s and 9,830.4 Mb/s

X-Ref Target - Figure 3-13

iq_transmit_9830.jpg
Figure 3-14: 32-Bit Wide Receive Interface at 8,110.08 Mb/s and 9,830.4 Mb/s

X-Ref Target - Figure 3-14

iq_receive_9830.jpg

When the core is configured to run at 10,137.6 Mb/s, the 32 bit I/Q data bus is used. As with 8,110.08 Mb/s and 9,830.4 Mb/s, the control word is 16 bytes long. The basic frame is extended to be 80 clock periods long. This Figure and This Figure illustrate the I/Q transmit and receive interfaces at 10,137.6 Mb/s.

Figure 3-15: 32-Bit Transmit Interface at 10,137.6 Mb/s

X-Ref Target - Figure 3-15

AdJjy3X5_t.jpg
Figure 3-16: 32-Bit Receive Interface at 10,137.6 Mb/s

X-Ref Target - Figure 3-16

aH2ldHph_t.jpg

When the core is configured to run at 12,165.12 Mb/s, the 32-bit I/Q data bus is used. As with 8,110.08, 9,830.4, and 10,137.6 Mb/s the control word is 16 bytes long. The basic frame is extended to be 96 clock periods long. This Figure and This Figure illustrate the I/Q transmit and receive interfaces at 12,165.12 Mb/s.

Figure 3-17: 32-Bit Transmit Interface at 12,165.12 Mb/s

X-Ref Target - Figure 3-17

32-bit-tx-12G-6zXQMtcF_t.jpg
Figure 3-18: 32-Bit Receive Interface at 12,165.12 Mb/s

X-Ref Target - Figure 3-18

vwM6lSMF_t.jpg

When the core is configured to run at 24,330.24 Mb/s a 64-bit I/Q data bus is used. The basic frame at the highest speed is 96 cycles long. The 24,330.24 Mb/s core can also operate at 12,165.12 Mb/s and 8,110.08 Mb/s. At these speeds the basic frame is 48 and 32 cycles long respectively. The control word is always 16 bytes long. This Figure and This Figure show the I/Q transmit and receive interfaces at 24,330.24 Mb/s.

Figure 3-19: 64-Bit Transmit Interface at 24,330.24 Mb/s

X-Ref Target - Figure 3-19

64bit-tx-24G-ozWamALS_t.jpg
Figure 3-20: 64-Bit Receive Interface at 24,330.24 Mb/s

X-Ref Target - Figure 3-20

Xj_R8TD8_t.jpg