Shared Logic - 8.11 English

The Shared Logic tab is not available on Versal ACAP cores. This Figure shows the Vivado IDE Shared Logic tab of the CPRI core.

Figure 5-3: CPRI Main Screen - Shared Logic Tab

X-Ref Target - Figure 5-3

If the shared logic is included in the core the common clocking and transceiver logic for the CPRI core is generated in a support layer around the core. See Example Design .