Hard FEC Variable Latency Register (0x20) - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English

When using Hard FEC enabled CPRI cores, this register provides the variable component of the latency through the Hard FEC. Each time the Hard FEC achieves alignment on a CPRI channel the latency through the Hard FEC will settle on a different value. This is an unavoidable feature of the FEC alignment process. This register provides a means of reading the variable part of this latency and can be used to perform the delay measurement calculation for requirement R21 in hardware. The variable part of the latency is also provided by an output port as shown in Table: Status Interface Signals . The fixed component of the Hard FEC latency is documented in the Additional Pipeline Delays section.

Table 2-32:

Bits

Description

31:16

Reserved

15:0

Hard FEC Variable Latency (in integer clock cycles)

Hard FEC Variable Latency Register