Delay Through the GTYE4 Transceiver - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English

Delay through the GTYE4 transceiver consists of a variable component (barrel shift or TX and RX gearbox latency) and a fixed component. The fixed component is made up of the delay shown in Table: Fixed Contribution to Delay - GTYE4 Transceiver plus the additional line rate delay shown below.

Table 4-13: Fixed Contribution to Delay - GTYE4 Transceiver

Block

Latency (UI)

TX

16-bit datapath cores (8b/10b)

159

32-bit datapath cores (8b/10b)

169

32-bit datapath cores (64b/66b)

190

64-bit datapath cores (64b/66b)

352

RX

16-bit datapath cores (8b/10b)

132.5

32-bit datapath cores (8b/10b)

242.5

32-bit datapath cores (64b/66b)

117.5

64-bit datapath cores (64b/66b)

213.5