The datapath clocks are generated in the clocking block in the core support layer. This leads to some differences in the core level clocking ports between designs that are generated with the core support layer and those that are generated without. For more information on the core support layer see CPRI Core Structure .
Table: Clock and Reset Signals (All Cores) lists the clock and reset ports that are common to both support layer configurations of the core.
|
Port |
Direction |
Description |
|---|---|---|
|
reset |
In |
Active-High asynchronous reset for the core. This reset is synchronized to each clock domain inside the core. It does not reset the management configuration registers. The core can also be reset using a soft reset (see General Configuration and Transmit CPRI Alarms Register (0xE) ). Soft reset also does not reset the management configuration registers. |
|
refclk |
In |
Transceiver reference clock input. Generated from the transceiver differential reference clock input by an IBUFDS in the user design. |
|
tx_refclk |
In |
Artix®-7 cores supporting a free running receive clock only. Transceiver reference clock input from a crystal oscillator by an IBUFDS. Used to drive PLL1 in the GTPE2_COMMON component. |
|
aux_clk/
|
In |
Management clock in the range 5-125 MHz. When the AXI4-Lite Management Interface option is selected, the management interface is clocked by the s_axi_aclk input from the AXI4-Lite bus. When the generic management interface is used, the aux_clk input is used to clock the management interface. See Customizing and Generating the Core for more information. In addition to the management interface this clock also drives the blocks programming the Dynamic Reconfiguration Port (DRP) ports of the GT transceiver and the internal Phase-Locked Loops (PLLs) used for clock synthesis. This clock must run continuously without interruption as the GT transceiver and PLLs are reconfigured during speed switches. This clock can be shared between multiple instances of the CPRI core. |
|
reset_aux_clk/
|
In |
Management Interface reset. Asserting this signal resets the management sections of the design.
|
|
gtwiz_reset_clk_
|
In |
UltraScale™ architecture-based devices only. Clock for the transceiver reset state machine in the core. This free running clock must have a frequency lower than that of the system clock when running at the lowest supported line rate, for example 15.36 MHz for 32-bit cores supporting 614.4 Mb/s. This clock can be shared between multiple cores. |
|
hires_clk |
In |
High resolution sampling clock used to measure the transit time of the clock-domain crossing FIFO(s). Must be at least
150 MHz when operating at speeds of 2,457.6 Mb/s and under
The clock should not be derived from the same source as refclk ; it must be unrelated. This clock can be shared between multiple instances of the CPRI core. |
|
hires_clk_ok |
In |
High resolution clock OK. Signal indicating the status of the high resolution clock. Set High when the clock is stable. |
|
eth_ref_clk |
In |
Ethernet clock running at 25 MHz. When the MII interface is selected, this clock is used to clock the Ethernet interface. This should also be used to clock the client logic attached to this interface. |
|
eth_tx_clk |
In |
Ethernet transmit clock running at 125 MHz. When the GMII interface is selected, this clock is used to clock the transmit side of the Ethernet interface. This should also be used to clock the client logic attached to the transmit interface. |
|
eth_rx_clk |
In |
Ethernet receive clock running at 125 MHz. When the GMII interface is selected, this clock is used to clock the receive side of the Ethernet interface. This should also be used to clock the client logic attached to the receive interface. |
|
rxrecclkout |
Out |
In UltraScale and UltraScale+ based designs the RXRECCLKOUT port of the transceiver can be routed out of the device directly. This port can be connected to an OBUFDS_GTE3 or OBUFDS_GTE4 as shown in the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 4] and the UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 5] |
Table: Clock and Reset Signals (Support Layer Generated in the Core) lists the clock and reset ports that are exclusive to designs generated with the core support layer. These are generated by the clocking circuitry in the support layer and output for use in the user design. The clocks from the PLL in the common block are also routed out of the core. These can be shared by other transceivers in the quad. See Transceiver Interface (UltraScale and 7 Series Cores Only) for a description of these clocks.
|
Port |
Direction |
Description |
|---|---|---|
|
refclk_307 |
In |
Transceiver 307.2 MHz reference clock input. In 7 series and GTHE3-based cores that support 12,165.12 Mb/s a second reference clock is required in order to support all the line rates. |
|
clk_out |
Out |
System clock. Used for all datapath logic in the core and to clock the I/Q, frame and synchronization, HDLC and vendor-specific interfaces. The same clock should be used to clock client logic attached to these interfaces. See Table: Client Clock Rates for the core clock rates. |
|
clk_ok_out |
Out |
System clock OK. Signal indicating the status of the system clock. High when the clock is stable. |
|
recclk |
Out |
Recovered clock from the GT transceiver. When the design is operating as a slave, a clean-up PLL should be used to generate the transceiver reference clock from the recclk output. |
|
recclk_ok |
Out |
Recovered clock OK. Signal indicating the status of the recovered clock. High when the clock is stable. |
|
txusrclk_out |
Out |
Artix-7 and 24,330.24 Mb/s capable UltraScale and UltraScale+ based cores only. Transceiver TXUSRCLK input. Clock running at double the speed of clk_in. See Clock Configuration . |
|
rx_rec_clk_ch(x) |
In |
Recovered clocks from the GTs within the three external CPRI lanes (1,2,3) which are sharing the Hard FEC. The recovered clocks are used to write 66-bit data & header into the Hard FEC CDC FIFOs. |
|
cdc_reset_ch(x) |
In |
Hard FEC capable cores only. CDC reset from each CPRI lane (1,2,3) to the Hard FEC. Hold CDC FIFO in reset until clocks are stable. |
|
pcs_txclk_ch(x) |
Out |
Hard FEC capable cores only. System Clock from the Hard FEC within the host CPRI core to the external CPRI lanes (1,2,3). The Hard FEC output data and header is synchronous to this clock. |
|
pcs_txclk_ok_ch(x) |
Out |
Hard FEC capable cores only. System clock ok from Hard FEC within the host CPRI core to the external CPRI lanes (1,2,3). |
Table: Clock and Reset Signals (Support Layer Generated in the Example Design) lists the clock and reset ports that are exclusive to designs generated with the core support layer in the example design rather than in the core. The clock inputs are generated by the clocking circuitry in the support layer. The core also outputs some clocks and control signals to the clocking block. The clocks from the PLL in the common block are also routed in to the core. See Transceiver Interface (UltraScale and 7 Series Cores Only) for a description of these clocks.
|
Port |
Direction |
Description |
|---|---|---|
|
txoutclk |
Out |
Transmit output clock from the GT transceiver. This is used to generate the system clock. |
|
clk_in |
In |
System clock. Used for all datapath logic in the core and to clock the I/Q, frame and synchronization, HDLC and vendor-specific interfaces. The same clock should be used to clock client logic attached to these interfaces. See Table: Client Clock Rates for the core clock rates. |
|
clk_316_in |
In |
Present on GTXE2 and GTHE2 implementations supporting 10,137.6 or 12,165.12 Mb/s only. This is the transceiver TX user clock. At line rates using 8B10B encoding it runs at the same frequency as clk_in. When 64B66B encoding is enabled it runs at 66/64th of the clk_in frequency.
At 12,165.12 Mb/s the frequency is 380.16 MHz;
See Clock Configuration . |
|
txusrclk |
In |
Artix-7 and 24,330.24 Mb/s capable UltraScale and UltraScale+ based cores only. Transceiver TXUSRCLK input. Clock running at double the speed of clk_in . See Clock Configuration . |
|
clk_ok_in |
In |
System clock OK. Signal indicating the status of the system clock. Drive High when the clock is stable. |
|
rxoutclk |
Out |
Receive output clock from the GT transceiver. This is used to generate the recovered clock input. |
|
recclk_in |
In |
Recovered clock input for the GT transceiver. |
|
recclk_ok |
Out |
Recovered clock OK. Signal indicating the status of the recovered clock. High when the transceiver has completed receiver reset and alignment. |
|
mmcm_rst |
Out |
MMCM Reset. A High on this signal holds the MMCM in the clocking block in reset until
txoutclk
is stable.
|
|
txresetdone_out |
Out |
Present on the UltraScale and UltraScale+ implementations. Signal from the core indicating that the transceiver reset sequence is complete. The core is held in reset until this signal is asserted. |
|
gtreset_sm_done |
Out |
Present on GTHE2 and GTPE2 implementations. Signal from the core indicating that the transceiver reset sequence is complete. This is used by the clocking block to prevent a speed change during a reset cycle. |
|
userclk_tx_reset |
Out |
Present in GTHE3/GTYE3/GTHE4/GTYE4 implementations only. Reset for the transmit clock BUFG_GT in the clocking logic. |
|
userclk_rx_reset |
Out |
Present in GTHE3/GTYE3/GTHE4/GTYE4 implementations only. Reset for the receive clock BUFG_GT in the clocking logic. |
|
rx_rec_clk_ch |
Out |
Recovered clock output to the Hard FEC in the host CPRI core. The recovered clock is used to write 66-bit data & header into the Hard FEC CDC FIFO. |
|
cdc_reset_ch |
Out |
CDC reset to the Hard FEC in the host CPRI core. Hold CDC FIFO in reset until clocks are stable. |
|
pcs_txclk_ch |
In |
Hard FEC output clock. The output data and header is synchronous to this clock. |
|
pcs_txclk_ok_ch |
In |
Hard FEC output clock ok. |
|
Port |
Direction |
Description |
|---|---|---|
|
rx_fast_reset |
In |
Hard FEC wrapper reset. Active-High input. |
|
rx_fast_clk |
In |
In Hard FEC Wrapper cores this is the main 368.64 MHz input clock to the Hard FEC. It is used on the ingress and egress 66-bit datapaths of the Hard FEC and sources the pcs_txclk_ch(0,1,2,3) outputs from the Hard FEC to the four CPRI interfaces. • 368.64 MHz for 24.3G Hard FEC wrapper cores • 184.32 MHz for 12.1G cores • 153.6 MHz for 10.1G cores • 122.88 MHz for 8.1G cores |
|
rsfec_clk |
In |
In Hard FEC wrapper cores this is the RS-FEC clock input: • 294.912 MHz for 24.3G Hard FEC wrapper cores • 184.32 MHz for 12.1G cores • 153.6 MHz for 10.1G cores • 122.88 MHz for 8.1G cores • For 24.3G Hard FEC cores, this clock should be generated from the rx_fast_clk (368.64 MHz). • For 12.1G, 10.1G and 8.1G Hard FEC cores, this clock should be the same as the rx_fast_clk. |
|
hires_clk |
In |
High resolution sampling clock used to measure the transit time of the clock-domain crossing FIFOs. Must be at least 380 MHz for operation at 24,330.24 Mb/s. |
|
all_clk_locked |
In |
Assert high when rx_fast_clk, rsfec_clk and hires_clk input clocks are all stable. |
|
rx_rec_clk_ch(x) |
In |
Recovered clock inputs from the GTs within each of the 4 CPRI lanes (0,1,2,3). The recovered clocks are used to write 66-bit data & header into the Hard FEC CDC FIFOs. |
|
cdc_reset_ch(x) |
In |
CDC reset from each CPRI lane (0,1,2,3). Hold CDC FIFO in reset until clocks are stable. |