If the CPRI core supports operation at 4,915.2 Mb/s or over, a GMII interface option is available. The GMII Ethernet interface on the CPRI core is designed to appear as an GMII-compliant PHY interface; therefore, it can be directly connected to a 1 Gb or tri-speed Ethernet MAC (such as the Xilinx Ethernet MAC core).
Standard GMII interfacing is used, as shown in
Table: Ethernet Interface Signals, GMII Interface
,
This Figure
, and
This Figure
.
Table 3-22:
Ethernet Interface Signals, GMII Interface
|
Port
|
Direction
|
Clock Domain
|
Description
|
|
eth_txd[7:0]
|
In
|
Ethernet Transmit Clock
|
Ethernet transmit data
|
|
eth_tx_en
|
In
|
Ethernet Transmit Clock
|
Ethernet transmit enable
|
|
eth_tx_er
|
In
|
Ethernet Transmit Clock
|
Ethernet transmit error
|
|
eth_rxd[7:0]
|
Out
|
Ethernet Receive Clock
|
Ethernet receive data
|
|
eth_rx_dv
|
Out
|
Ethernet Receive Clock
|
Ethernet receive data valid
|
|
eth_rx_er
|
Out
|
Ethernet Receive Clock
|
Ethernet receive data error
|
|
eth_rx_ready
|
In
|
Ethernet Receive Clock
|
Signal from the client to the CPRI core indicating that it is ready to receive Ethernet frames. Tie High if no flow control required.
|
|
eth_rx_avail
|
Out
|
Ethernet Receive Clock
|
Signal from the CPRI core indicating that it has at least one Ethernet frame ready to send to the client. Leave open if no flow control is required.
|
|
rx_fifo_almost_full
|
Out
|
Ethernet Receive Clock
|
CPRI receive Ethernet FIFO is over 62.5% full
|
|
rx_fifo_full
|
Out
|
Ethernet Receive Clock
|
CPRI receive Ethernet FIFO is full
|
|
eth_col
|
Out
|
Async
|
Ethernet collision detect. Asserted when the TX FIFO is full or if both the RX and TX interfaces are active and the “Ethernet Transmitter Ignores RX_DV” bit in the General Configuration and Transmit CPRI Alarms register is set to zero.
|
|
eth_crs
|
Out
|
Async
|
Ethernet carrier sense. Asserted when the TX interface is active or the Ethernet FIFO is over 62.5% full. In addition this signal is asserted when the RX interface is active and the “Ethernet Transmitter Ignores RX_DV” bit in the General Configuration and Transmit CPRI Alarms register is set to zero.
|
The example design delivered with the core contains a GMII interface to an external Ethernet MAC. See
Using an External GMII Interface
. If the core is interfacing to an on-chip Ethernet MAC, the
eth_tx_clk
and
eth_rx_clk
ports can be connected together and driven from a 125 MHz reference clock.
The CPRI core asserts the
eth_rx_avail
output when there is a frame present in the Ethernet receive FIFO. This can be used to enable the client logic. In addition the client can assert the
eth_rx_ready
input to the core when it is ready to accept data. When this signal is not asserted, the Ethernet frames are stored in the FIFO rather than being output to the client.
If the GMII mode field in the
General Configuration and Transmit CPRI Alarms Register (0xE)
management register is set to 0 then 4-bit wide MII data is transmitted over the GMII interface synchronous to
eth_tx_clk
. Bits 4 to 7 of
gmii_txd
are ignored. MII data is output on the receive ports synchronous to
eth_rx_clk
. Bits 4 to 7 of
gmii_rxd
are set to 0.
X-Ref Target - Figure 3-58
Figure 3-58:
Transmit GMII Ethernet Timing Showing a Collision
|
|
X-Ref Target - Figure 3-59
Figure 3-59:
Receive GMII Ethernet Timing Showing an Error Due to a Collision
|
|
