FEC Status Register (0x1B) - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English
Table 2-27: FEC Status Register

Bits

Description

31:11

Reserved

10:8

stat_symbol_errors

Indicates the number of symbol errors corrected in each codeword. (1)

7:1

stat_rx_delay

Indicates the fraction of a clock cycle delay that is added to the RX datapath latency by the FEC input gearbox. A value of 0 means no additional delay, a value of 65 means 65/66 of a clock cycle is being added. (1)

0

stat_rx_align_status

When High this signal indicates that alignment to the incoming codeword boundary position has been achieved and the receiver is accepting and processing data.

Notes:

1. Not available on optional 100G Ethernet RS-FEC hardened block.